CS7620 Datasheet, PDF (65/70 Pages) Cirrus Logic – CCD IMAGER ANALOG PROCESSOR

CS7620
5.1 Supply
VDDA[1:2] - Supply for analog
Pins 25 and 40
5 V analog supply.
VDDA3 - Supply for horizontal outputs
Pin 32
3.3 V or 5 V analog supply.
VDDD - Supply for digital
Pin 5
5 V digital supply.
VDD_RING - supply for pad ring (digital pads)
Pin 11
3.3 V or 5 V digital supply
5.2 Ground
GNDA[1:2] - Ground for analog
Pins 24 and 41
GNDA1 and GNDA2 are supplied by VDDA1 and VDDA2 respectively.
GNDA3 - Ground for horizontal outputs
Pin 31
Supplied by VDDA3.
GNDD - Ground for digital
Pin 4
Supplied by VDDD.
GND_RING - Ground for pad ring (digital pads)
Pin 10
Supplied by VDD_RING.
5.3 CMOS Input
BYPASS_PLL - Powers down PLL if not in use
Pin 39
Supplied by VDDA2.
CLAMP - Black level clamp signal
Pin 2
Only used if an external timing generator is used. Supplied by VDD_RING.
CLOCK_IN - Chip input clock
Pin 43
Supplied by VDDA2.
EXPOSE - Begin expose sequence
Pin 14
Expose signal from the shutter. Supplied by VDD_RING.
LINE_ENA - Line enable signal
Pin 3
Supplied by VDD_RING.
PWR_DN - Places chip in full power down
Pin 15
Supplied by VDD_RING.
REF_CAPN - Reference capacitor- negative terminal
Pin 27
Supplied by VDDA1. A 1 µF ceramic capacitor should be connected between
REF_CAPN and REF_CAPP.
REF_CAPP - Reference capacitor- positive terminal
Pin 28
Supplied by VDDA1. A 1 µF ceramic capacitor should be connected between
REF_CAPN and REF_CAPP.
DS301PP2
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