SA57 Datasheet, PDF (6/14 Pages) Cirrus Logic – Switching Amplifier

SA57
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Table 1. Pin Descriptions
Pin #
Pin Name
Signal Type
5,9,11,13 SGND
Power
15
1b
Logic Input
17
1t
Logic Input
19
V_DD
21
I1
Power
Analog Output
23
DIS2
Logic Input
25
TEMP
Logic Output
46,47,48,49 V_S (phase 2)
33,34,35
OUT 1
Power
Power Output
37,38,39,40 PGND (phase 1) Power
26,27,58,59 HS
Mechanical
2,4,6,8,10,
12,14,16,18,
20,22,24,28,
32,36,41,42,
NC
---
43,44,45,50,
54,60,62,64
Simplified Pin Description
Analog and digital GND – internally connected to PGND
Logic high commands 1 phase lower FET to turn on
Logic high commands 1 phase upper FET to turn on
Logic Supply (5V)
Phase 1 current sense output
Logic high places all outputs in a high impedance state
Thermal indication of die temperature above 135ºC
High Voltage Supply phase 2
Half Bridge 1 Power Output
High Current GND Return Path for Power Outputs 1&2
Pins connected to the package heat slug
Do Not Connect
1.2 Pin Descriptions
V_S: Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency
characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the V_S
and PGND pins as possible. Additional capacitance will be required at the V_S pins to handle load current peaks and
potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding
bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply
current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B & C supply pins
(46-49) are monitored for undervoltage conditions.
OUT 1, OUT 2: These pins are the power output connections to the load. NOTE: When driving an inductive load, it
is recommended that two Schottky diodes with good switching characteristics (fast t_RR specs) be connected to each
pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PGND: Power Ground. This is the ground return connection for the output FETs. Return current from the load flows
through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of
this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resis-
tor.
1b, 2b: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-
channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry
will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also in-

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