CS61535A Datasheet, PDF (5/48 Pages) Cirrus Logic – T1/E1 LINE INTERFACE

CS61535A
ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Driver Performance Monitor
MTIP/MRING Sensitivity:
Differential Voltage Required for Detection
-
0.60
-
V
Receiver
RTIP/RRING Input Impedance
-
50k
-
Ω
Sensitivity Below DSX (0dB = 2.4V)
-13.6
-
-
dB
Data Decision Threshold
T1, DSX-1
(Note 24)
60
65
70
% of peak
T1, DSX-1
(Note 25)
53
65
77
% of peak
T1, FCC Part 68 and E1
(Note 26)
45
50
55
% of peak
Data Decision Threshold
T1
-
65
-
% of peak
E1
-
50
-
% of peak
Allowable Consecutive Zeros before LOS
160
175
190
bits
Receiver Input Jitter Tolerance
(Note 27)
10kHz - 100kHz
2kHz
10Hz and below
0.4
-
6.0
-
300
-
-
UI
-
UI
-
UI
Loss of Signal Threshold
(Note 28) 0.25
0.30
0.50
V
Notes: 24. For input amplitude of 1.2 V_pk to 4.14 V_pk.
25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
26. For input amplitude of 1.05 Vpk to 3.3 Vpk.
27. Jitter tolerance increases at lower frequencies. See Figure 11.
28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and
RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data
decision threshold. The analog input squelch circuit operates when the input signal amplitude above
ground on the RTIP and RRING pins falls within the squelch range long enough for the internal
slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on
RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses
greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing
less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993.
DS40F2
5