CS42436 Datasheet, PDF (47/66 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 6-out TDM CODEC

Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC2.
+6 dB digital gain is automatically applied to the serial audio data of ADC2. The negative leg must be
driven to the common mode of the ADC. See Figure 21 on page 52 for a graphical description.
7.6.6 ADC3 SINGLE-ENDED MODE (ADC3 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC
1 - Enabled; Single-Ended input to ADC
Function:
When disabled, this bit removes the 4:2 multiplexer from the signal path of ADC3 allowing a differen-
tial input. When enabled, this bit allows the user to choose between 4 single-ended inputs to ADC3,
using the AIN5_MUX and AIN6_MUX bits. See Figure 10 on page 29 and Figure 21 on page 52 for
graphical descriptions.
7.6.7 ANALOG INPUT CH. 5 MULTIPLEXER (AIN5_MUX)
Default = 0
0 - Single-Ended Input AIN5A
1 - Single-Ended Input AIN5B
Function:
ADC3 can accept single-ended input signals when the ADC3 SINGLE bit is enabled. The AIN5_MUX
bit selects between two input channels (AIN5A or AIN5B) to be sent to ADC3 in single-ended mode.
This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 10 on page 29 for a graphical
description.
7.6.8 ANALOG INPUT CH. 6 MULTIPLEXER (AIN6_MUX)
Default = 0
0 - Single-Ended Input AIN6A
1 - Single-Ended Input AIN6B
Function:
ADC3 can accept a single-ended input signal when the ADC3 SINGLE bit is enabled. The AIN6_MUX
bit selects between two input channels (AIN6A or AIN6B) to be sent to ADC3 in single-ended mode.
This bit is ignored when the ADC3_SINGLE bit is disabled. See Figure 10 on page 29 for a graphical
description.
7.7 TRANSITION CONTROL (ADDRESS 06H)
7
6
DAC_SNGVOL DAC_SZC1
5
DAC_SZC0
4
AMUTE
3
2
1
MUTE ADC_SP ADC_SNGVOL ADC_SZC1
7.7.1 SINGLE VOLUME CONTROL (DAC_SNGVOL, ADC_SNGVOL)
Default = 0
0
ADC_SZC0
DS647PP2
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