WM8255 Datasheet, PDF (42/49 Pages) Cirrus Logic – Single Channel 16-bit CIS/CCD AFE with RGB LED Current Drive

Production Data
REGISTER BIT
NO
Setup
0
Register 2
1
2
3
4
5
7:6
Setup
3:0
Register 3
5:4
7:6
Software
Reset
BIT NAME(S)
POSNEG
2BITOP
INVOP
VRLCEXT
RLCINT
Reserved
DEL[1:0]
RLCV[3:0]
CDSREF[1:0]
INTM[1:0]
DEFAULT
DESCRIPTION
WM8255
0
0
0
0
0
0
00
0011
01
00
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate
internal timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate
internal timing pulse.
See Figure 27 for further details.
Changes the digital output from 4 bit muxed to 2 bit muxed output.
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
When set powers down the RLCDAC, changing its output to Hi-Z,
allowing VRLC/VBIAS to be externally driven.
This bit is used to determine whether Reset Level Clamping is enabled.
0 = RLC disabled, 1 = RLC enabled.
Must be set to zero.
Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC
clock period = 3 MCLK periods.
00 = Minimum latency
01 = Delay by one ADC clock
period
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock periods
Controls RLCDAC driving VRLC pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical
Characteristics section for ranges.
CDS mode reset timing adjust.
00 = Advance 1 MCLK period 10 = Retard 1 MCLK period
01 = Normal
11 = Retard 2 MCLK periods
Colour selection bits used in internal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 1 for details.
Any write to Software Reset causes all cells (including LED) to be reset.
It is recommended that a software reset be performed after a power-up
before any other register writes.
Setup
2:0
VDEL[2:0]
Register 4
5:3
Reserved
000
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 27, Internal VSMP Pulses Generated for details.
000
Must be set to zero
Setup
Register 5
Setup
Register 6
Setup
Register 7
Setup
Register 8
6
LEDIMAX
0
7
Reserved
0
7:0 LEDIDACR [7:0] 00100000
Sets the maximum current limit to one of two ranges (see electrical
characteristics section).
Must be set to zero
Fine LED current during imaging for Red LED
7:0 LEDIDACG [7:0] 00100000 Fine LED current during imaging for Green LED
7:0 LEDIDACB [7:0] 00100000 Fine LED current during imaging for Blue LED
1:0 LEDIRNGR [1:0]
00
Coarse LED current range during imaging for Red LED
2
Reserved
0
Must be set to zero
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PD, Rev 4.7, August 2013
42