CS4299-BQ Datasheet, PDF (40/52 Pages) Cirrus Logic – CrystalClear SoundFusion Audio Codec 97

CS4299-BQ
7. SONY/PHILIPS DIGITAL
INTERFACE (S/PDIF)
The S/PDIF digital output is used to interface the
CS4299-BQ to consumer audio equipment external
to the PC. This output provides an interface for
storing digital audio data or playing digital audio
data to digital speakers. Figure 20 illustrates the
circuits necessary for implementing the IEC-958
optical or consumer interface. For further informa-
tion on S/PDIF operation see application note
AN22: Overview of Digital Audio Interface Data
Structures [3]. For further information on S/PDIF
recommended transformers see application note
AN134: AES and S/PDIF Recommended Trans-
formers [4].
8. GROUNDING AND LAYOUT
Figure 21 on page 41 shows the conceptual layout
for the CS4299-BQ. The decoupling capacitors
should be located physically as close to the pins as
possible. Also note the connection of the REFFLT
decoupling capacitors to the ground return trace
connected directly to the ground return pin, AVss1.
It is strongly recommended that separate analog
and digital ground planes be used. Separate ground
planes keep digital noise and return currents from
modulating the CS4299-BQ ground potential and
degrading performance. The digital ground pins
should be connected to the digital ground plane and
kept separate from the analog ground connections
of the CS4299-BQ and any other external analog
circuitry. All analog components and traces should
be located over the analog ground plane and all dig-
ital components and traces should be located over
the digital ground plane.
The common connection point between the two
ground planes (required to maintain a common
ground voltage potential) should be located under
the CS4299-BQ. The AC-link digital interface con-
nection traces should be routed such that the digital
ground plane lies underneath these signals (on the
internal ground layer). This applies along the entire
length of these traces from the AC ’97 controller to
the CS4299-BQ.
Refer to the Application Note AN18: Layout and
Design Rules for Data Converters and Other
Mixed Signal Devices [2] for more information on
layout and design rules.
S/PDIF_OUT ^R1
SPDIF_OUT
R₂
DVdd 3.3V 5V
R₁ 247.5 Ω 375 Ω
R₂ 107.6 Ω 93.75 Ω
DGND
J1
T₁
+5V_PCI
0.1 µ F
SPDIF_OUT ⁴
3
8.2 kΩ ₂
1
5
DGND
6
DGND
TOTX-173 _DGND
Figure 20. S/PDIF Output
40