SA03 Datasheet, PDF (4/5 Pages) Cirrus Logic – PULSE WIDTH MODULATION AMPLIFIER

SA03
Product Innova tionFrom
GENERAL
Please read Application Note 30 on "PWM Basics". Refer
to Application Note 1 "General Operating Considerations" for
helpful information regarding power supplies, heat sinking
and mounting. Visit www.Cirrus.com for design tools that help
automate pwm filter design; heat sink selection;Apex Precision
Power’s complete Application Notes library;Technical Seminar
Workbook; and Evaluation Kits.
CLOCK CIRCUIT AND RAMP GENERATOR
The clock frequency is internally set to a frequency of ap-
proximately 45kHz. The CLK OUT pin will normally be tied
to the CLK IN pin. The clock is divided by two and applied to
an RC network which produces a ramp signal at the –PWM/
RAMP pin. An external clock signal can be applied to the CLK
IN pin for synchronization purposes. If a clock frequency lower
than 45kHz is chosen an external capacitor must be tied to the
–PWM/RAMP pin. This capacitor, which parallels an internal
capacitor, must be selected so that the ramp oscillates 4 volts
p-p with the lower peak 3 volts above ground.
PWM INPUTS
The full bridge driver may be accessed via the pwm input
comparator. When +PWM > -PWM then A OUT > B OUT. A
motion control processor which generates the pwm signal can
drive these pins with signals referenced to GND.
PROTECTION CIRCUITS
In addition to the externally programmable current limit there
is also a fixed internal current limit which senses only the high
side current. It is nominally set to 140% of the continuous
rated output current. Should either of the outputs be shorted
to ground the high side current limit will latch off the output
transistors. Also, the temperature of the output transistors is
continually monitored. Should a fault condition occur which
raises the temperature of the output transistors to 165°C the
thermal protection circuit will activate and also latch off the
output transistors. In either case, it will be necessary to remove
the fault condition and recycle power to V_CC to restart the circuit.
CURRENT LIMIT
There are two load current sensing pins, I SENSE A and I
SENSE B. The two pins can be shorted in the voltage mode
connection but both must be used in the current mode connec-
tion (see figures A and B). It is recommended that R_LIMIT resistors
be non-inductive. Load current flows in the I SENSE pins. To
avoid errors due to lead lengths connect the I LIMIT/SHDN pin
directly to the R_LIMIT
resistors (through I SENSE A
the filter network
and shutdown di-
vider resistor) and ^{I SENSE B}
R _LIMIT
connect the R_LIMIT
resistors directly to
the GND pin.
I LIMIT/SHDN _{R FILTER}
1K _SHUTDOWN
SIGNAL
Switching noise
spikes will invariably
C _FILTER
R _SHDN
be found at the I
SENSE pins. The
FIGURE A. CURRENT LIMIT WITH
SHUTDOWN VOLTAGE MODE.
I SENSE A
1K
noise spikes could trip the cur-
rent limit threshold which is only
R _LIMIT
100 mV. R_FILTER and C_FILTER should
be adjusted so as to reduce the
I SENSE B
1K
switching noise well below 100
mV to prevent false current limit-
R _LIMIT
ing.The sum of the DC level plus
the noise peak will determine
I LIMIT/SHDN _{R FILTER}
the current limit-
SHUTDOWN
SIGNAL
ing value. As in
most switching
C _FILTER
R _SHDN
circuits it may
be difficult to de-
FIGURE B. CURRENT LIMIT WITH
SHUTDOWN CURRENT MODE.
termine the true
noise amplitude
without careful attention to grounding of the oscilloscope probe.
Use the shortest possible ground lead for the probe and con-
nect exactly at the GND terminal of the amplifier. Suggested
starting values are C_FILTER = .01uF, R_FILTER = 5k .
The required value of R_LIMIT in voltage mode may be cal-
culated by:
R_LIMIT = .1 V / I_LIMIT
where R_LIMIT is the required resistor value, and I_LIMIT is the
maximum desired current. In current mode the required value
of each R_LIMIT is 2 times this value since the sense voltage is
divided down by 2 (see Figure B). If R_SHDN is used it will further
divide down the sense voltage. The shutdown divider network
will also have an effect on the filtering circuit.
BYPASSING
Adequate bypassing of the power supplies is required for
proper operation. Failure to do so can cause erratic and low
efficiency operation as well as excessive ringing at the out-
puts. The Vs supply should be bypassed with at least a 1µF
ceramic capacitor in parallel with another low ESR capacitor
of at least 10µF per amp of output current. Capacitor types
rated for switching applications are the only types that should
be considered. The bypass capacitors must be physically
connected directly to the power supply pins. Even one inch of
lead length will cause excessive ringing at the outputs. This
is due to the very fast switching times and the inductance of
the lead connection. The bypassing requirements of the Vcc
supply are less stringent, but still necessary. A .1µF to .47µF
ceramic capacitor connected directly to the Vcc pin will suffice.
STARTUP CONDITIONS
The high side of the all N channel output bridge circuit is
driven by bootstrap circuit and charge pump arrangement. In
order for the circuit to produce a 100% duty cycle indefinitely
the low side of each half bridge circuit must have previously
been in the ON condition. This means, in turn, that if the input
signal to the SA03 at startup is demanding a 100% duty cycle,
the output may not follow the command and may be in a tri-
state condition. The ramp signal must cross the input signal
at some point to correctly determine the output state. After the
ramp crosses the input signal level one time, the output state
will be correct thereafter.
4
SA03U