CS61582 Datasheet, PDF (4/32 Pages) Cirrus Logic – DUAL T1/E1 LINE INTERFACE

DIGITAL CHARACTERISTICS (TA = -40 to 85 °C; power supply pins within ±5% of nominal)
Parameter
Symbol Min
Typ
Max Units
High-Level Input Voltage
(Note 7) VIH (DV+)-0.5 -
Low-Level Input Voltage
(Note 7) VIL
-
-
High-Level Output Voltage
(Digital pins)
IOUT = -40 µA
(Note 8) _{VOH (DV+)-0.3}
-
Low-Level Output Voltage
(Digital pins)
IOUT = 1.6 mA
(Note 8) _VOL
-
-
Input Leakage Current
(Digital pins except J-TMS, and J-TDI)
-
-
Notes: 7. Digital inputs are designed for CMOS logic levels.
8. Digital outputs are TTL compatible and drive CMOS levels into a CMOS load.
-
V
0.5
V
-
V
0.3
V
±10
µA
ANALOG SPECIFICATIONS (TA = -40 to 85 °C; power supply pins within ±5% of nominal)
Parameter
Min
Typ
Max Units
Receiver
RTIP/RRING Differential Input Impedance
-
20k
-
Sensitivity Below DSX-1 (0 dB = 2.4 V)
-13.6
-
-
Loss of Signal Threshold
-
0.3
-
Data Decision Threshold
T1, DSX-1
E1
(Note 9) 60
65
70
(Note 10) 55
-
75
(Note 11) 45
50
55
(Note 12) 40
-
60
Allowable Consecutive Zeros before LOS
160
175
190
Receiver Input Jitter
Tolerance (DSX-1, E1)
10 Hz and below
2 kHz
10 kHz - 100 kHz
(Note 13) 300
-
-
6.0
-
-
0.4
-
-
Receiver Return Loss
51 kHz - 102 kHz
(Notes 14, 12
-
-
102 kHz - 2.048 MHz
21, and 22) 18
-
-
2.048 MHz - 3.072 MHz
14
-
-
Jitter Attenuator
Jitter Attenuation Curve
T1
Corner Frequency
E1
(Notes 14 and 15)
-
4
-
-
5.5
-
Attenuation at 10 kHz Jitter Frequency
(Notes 14 and 15)
-
60
-
Attenuator Input Jitter Tolerance
(Note 14)
(Before Onset of FIFO Overflow or Underflow Protection)
28
43
-
Notes: 9. For input amplitude of 1.2 Vpk to 4.14 Vpk
10. For input amplitude of 0.5 Vpk to 1.2 Vpk, and 4.14 Vpk to 5.0 Vpk
11. For input amplitude of 1.07 Vpk to 4.14 Vpk,
12. For input amplitude of 4.14 Vpk to 5.0 Vpk,
13. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.
14. Not production tested. Parameters guaranteed by design and characterization.
15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance.
Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter
can increase significantly when more than 28 UI’s are input to the attenuator. Refer to the
Jitter Attenuator section.
Ω
dB
V
% of
Peak
bits
UI
UI
UI
dB
dB
dB
Hz
Hz
dB
UIpk-pk
4
DS224PP1