CS61884 Datasheet, PDF (38/72 Pages) Cirrus Logic – Octal T1/E1/J1 Line Interface Unit

CS61884
14.16 Global Control Register (0Fh)
BIT NAME
Description
This register is the global control for the AWG Auto-Increment, Automatic AIS insertion,
encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for
all eight channels. Register bits default to 00h after power-up or reset.
The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address
[7] AWG Auto- Register (17h) (See Section 14.24 on page 40) after each access. Thus, when this bit is set,
Increment the phase samples address portion of the address register increments after each read or
write access. This bit must be set before any bit in the AWG Enable register is set, if this
function is required.
On LOS, this bit controls the automatic AIS insertion into all eight receiver paths.
[6] RAISEN
0 = Disabled
1 = Enabled
[5]
RSVD
RESERVED (This bit must be set to 0.)
Line encoding/decoding Selection
[4] CODEN
0 = B8ZS/HDB3 (T1/J1/E1 respectively)
1 = AMI
Jitter Attenuator FIFO length Selection
[3]
FIFO
0 = 32 bits
LENGTH
1 = 64 bits
Jitter Attenuator Corner Frequency Selection
E1
T1/J1
[2]
JACF
0 = 1.25Hz
3.78Hz
1 = 2.50Hz
7.56Hz
These bits select the position of the Jitter Attenuator.
[1:0] JASEL [1:0]
JASEL 1
0
0
1
1
JASEL 0
0
1
0
1
POSITION
Disabled
Transmit Path
Disabled
Receive Path
14.17 Line Length Channel ID Register (10h)
BIT NAME
Description
[7:3] RSVD 7-3
RESERVED (These bits must be set to 0.)
The value written to these bits specify the LIU channel for which the Pulse Shape Configura-
tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs
[2:0] LLID 2-0 will select channel 0. The pulse shape configuration data for the channel specified in this reg-
ister are written or read through the Line Length Data Register (11h). Register bits default
to 00h after power-up or reset.
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