CS4329 Datasheet, PDF (3/36 Pages) Cirrus Logic – 20-Bit, Stereo D/A Converter for Digital Audio

CS4329
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Analog Output
Differential Full Scale Output Voltage
Output Common Mode Voltage
Differential Offset
AC Load Resistance
Load Capacitance
Symbol Min
Typ
(Note 5)
R_L
C_L
1.90
2.0
-
2.2
-
3
4
-
-
-
Max
2.10
-
15
-
100
Unit
Vrms
V
mV
kΩ
pf
Notes: 1. Triangular PDF Dithered Data
2. AUTO-MUTE active. See parameter definitions
3. The passband and stopband edges scale with frequency. For input sample rates, Fs, other than 48 kHz,
the passband edge is 0.4535×Fs and the stopband edge is 0.5465×Fs.
4. Group Delay for Fs=48 kHz 25/48 kHz=520 µs
5. Specified for a fully differential output ±((AOUT+)-(AOUT-)). See Figure 12.
SWITCHING CHARACTERISTICS (T_A= -10 to 70°C; Logic 0 = AGND = DGND; Logic 1 = VD = VA = 5.25
to 4.75 Volts; C_L = 20 pF)
Parameter
Input Sample Rate
MCLK Pulse Width High
MCLK / LRCK = 512
MCLK Pulse Width Low
MCLK / LRCK = 512
MCLK Pulse Width High
MCLK / LRCK = 384
MCLK Pulse Width Low
MCLK / LRCK = 384
MCLK Pulse Width High
MCLK / LRCK = 256
MCLK Pulse Width Low
MCLK / LRCK = 256
External SCLK Mode
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode
SCLK Period
SCLK / LRCK = 64
Symbol Min
Fs
1
10
10
21
21
31
32
t_sclkl
t_sclkh
t_sclkw
t_slrd
t_slrs
t_sdlrs
t_sdh
t_sclkw
20
20
1---2---8---1-(^--F----s---)
20
20
20
20
6---4----(^-1-F----s---)
Typ Max Unit
-
50
kHz
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
SDATA valid to SCLK rising setup time
t_{sdlrs 5---1---2---1-(--F----s---) + 10}
-
-
ns
SCLK rising to SDATA hold time MCLK / LRCK = 256 or 512 t_sdh
5---1---2---1-(^--F----s---) ^{+ 15}
-
-
ns
SCLK rising to SDATA hold time MCLK / LRCK = 384
t_sdh
3---8---4---1-(^--F----s---) ^{+ 15}
-
-
ns
DS153F1
3