CDB4354 Datasheet, PDF (3/11 Pages) Cirrus Logic – Evaluation Board for the CS4354

1. THE CDB4354 SYSTEM
CDB4354
The CDB4354 is a dedicated platform for evaluating the CS4354. The CS8416 digital audio interface receiver pro-
vides an easy interface to digital audio signal sources, including the majority of digital audio test equipment. The
evaluation board also allows the user to supply external PCM clocks and data directly to the CS4354 through a head-
er block for system development. In addition, hardware controls are available to test board and CS4354-specific fea-
tures.
The CDB4354 system block diagram and signal flow is shown in Figure 2. The CDB4354 schematics are shown in
Figures 3 and 4.
1.1 CS4354 Digital-to-Analog Converter
The CS4354 is a 24-bit, 2 V_RMS ground-centered output digital-to-analog converter with 101 dB (A-weight-
ed) dynamic range. A complete description of the CS4354 is included in the CS4354 datasheet.
1.2 CS8416 Digital Audio Receiver
The system receives and decodes the standard S/PDIF data format using a CS8416 Digital Audio Receiver.
The outputs of the CS8416 are standard PCM clocks and data: 256 Fs master clock, serial bit clock, left-
right clock, and serial data. The operation of the CS8416 and a discussion of the digital audio interface is
included in the CS8416 datasheet.
The evaluation board has been designed such that the active input can be either optical (OPT1) or coaxial
(J16). However, both inputs cannot be driven simultaneously.
1.3 Input for Serial Audio Clocks and Data
By default, the shunts on header block J6 are placed across columns 1 and 2, marked “SPDIF_RX”, which
routes the serial audio clocks and data from the CS8416 to the CS4354. This makes the S/PDIF inputs on
the evaluation board the default inputs. However, the user may remove these shunts and connect an exter-
nal source to columns 2 and 3 of header block J6, marked “EXT,” via a ribbon cable. Column 3 of J6 are
GND pins to maintain signal ground integrity when using external clocks and data.
Signals input to header J6 must be at the same voltage level as the VL supply on the evaluation board.
When using the S/PDIF inputs on the evaluation board with columns 1 and 2 of J6 shunted, this requirement
is always met and thus requires no precaution on the user’s part.
Please see the CS4354 datasheet for more information on clocking data into the CS4354.
Note:
If the VL supply is set to a low voltage level (VL<1.8 V), termination resistors may need to be added
to the J6 header signals to match the source and transmission-line impedances that are driving the
header. This may be accomplished by soldering resistors across the rows of J6 on the back of the
evaluation board.
1.4 Power Supply Circuitry
Power is supplied to the evaluation board by two binding posts, J2 (+5 V) and GND. The allowable input
voltage range for J2 is 4.75 V to 5.25 V. The VA supply for the CS4354 is sourced directly from the +5 V
supply. The VL supply can be sourced from either the +5 V supply or a +3.3 V regulated version, selected
using J12. Furthermore, the user can have full control over the VL supply voltage by removing the shunt
from J12, and connecting an external supply to pin 2 of J12. When using the S/PDIF inputs, the allowable
voltage range for pin 2 of J12 is 3.13 V to 5.25 V. When using external serial audio clocks and data, the
allowable voltage range for pin 2 of J12 is 1.4 V to 5.25 V.
DS895DB1
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