CS43L22_10 Datasheet, PDF (29/66 Pages) Cirrus Logic – Low Power, Stereo DAC w/Headphone & Speaker Amps

Confidential Draft
3/4/10
CS43L22
4.6 Serial Port Clocking
The CS43L22 serial audio interface port operates either as a slave or master, determined by the M/S bit. It
accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an
input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h
and 06h associated with a given MCLK and sample rate.
Referenced Control Register Location
M/S................................... “Master/Slave Mode” on page 40
Register 05h...................... “Clocking Control (Address 05h)” on page 38
Register 06h...................... “Interface Control 1 (Address 06h)” on page 40
MCLK
(MHz)
12.2880
11.2896
18.4320
(Slave
Mode
ONLY)
16.9344
(Slave
Mode
ONLY)
12.0000
24.0000
DS792F2
Sample Rate,
Fs (kHz)
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
11.0250
22.0500
44.1000
88.2000
8.0000
12.0000
16.0000
24.0000
32.0000
48.0000
96.0000
*8.0182...
11.0250
22.0500
44.1000
88.2000
8.0000
*11.0294...
12.0000
16.0000
*22.0588...
24.0000
32.0000
*44.1176...
48.0000
*88.2353...
96.0000
8.0000
*11.0294...
12.0000
16.0000
*22.0588...
24.0000
32.0000
*44.1176...
48.0000
*88.2353...
96.0000
SPEED[1:0]
(AUTO=’0’b)
11
11
10
10
01
01
00
11
10
01
00
11
11
10
10
01
01
00
11
11
10
01
00
11
11
11
10
10
10
01
01
01
00
00
11
11
11
10
10
10
01
01
01
00
00
32kGROUP
1
0
1
0
1
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
VIDEOCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RATIO[1:0]
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
10
00
00
00
00
01
11
01
01
11
01
01
11
01
11
01
01
11
01
01
11
01
01
11
01
11
01
MCLKDIV2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
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