CS5464 Datasheet, PDF (28/46 Pages) Cirrus Logic – Three-channel, Single-phase Power/Energy IC

CS5464
6. REGISTER DESCRIPTION
1. “Default” = bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
6.1 Page 0 Registers
6.1.1 Configuration (Config) Register
Address: 0
23
PC[7]
15
EWA
7
-
22
PC[6]
14
-
6
-
21
PC[5]
13
-
5
-
20
PC[4]
12
IMODE
4
iCPU
19
PC[3]
11
IINV
3
K[3]
18
PC[2]
10
-
2
K[2]
17
PC[1]
9
-
1
K[1]
16
PC[0]
8
-
0
K[0]
Default = 0x000001
PC[7:0]
Phase compensation. Sets a delay in the voltage channel relative to the current channel 1. De-
fault setting is 00000000 = 0.0215 degree phase delay at 60 Hz (when MCLK = 4.096 MHz).
EWA
Allows the E1 and E2 pins to be configured as open-collector output pins.
0 = Normal outputs (default)
1 = Only the pull-down device of the E1 and E2 pins are active
IMODE, IINV
Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
00 = Active-low level (default)
01 = Active-high level
10 = Low pulse
11 = High pulse
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising edge logic
K[3:0]
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero). K = 1 at reset.
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