CS42438_06 Datasheet, PDF (27/62 Pages) Cirrus Logic – 108 dB, 192 kHz 6-in, 8-out TDM CODEC

CS42438
Function
AIN6 Multiplexer
DAC Volume Control/Mute/Invert
ADC Volume Control
DAC Soft Ramp/Zero Cross
ADC Soft Ramp/Zero Cross
DAC Auto-Mute
Status Interrupt
Hardware Mode Feature Summary
Default Configuration
Hardware Control
Selects between AIN6A and
AIN6B when ADC3 in Single-
Ended Mode
“AIN6_MUX” pin 2
All DAC Volume = 0 dB, un-
muted, not inverted
-
All ADC Volume = 0 dB
-
Immediate Change
-
Immediate Change
-
Enabled
-
N/A
-
Table 2. Hardware Configurable Settings (Continued)
Note
see Section 5.2.2
-
-
-
-
-
-
5.2 Analog Inputs
5.2.1
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 9 on page 28 shows the full-scale analog input levels. The CS42438 also accommodates single-
ended signals on all inputs, AIN1-AIN6. See “ADC Input Filter” on page 50 for the recommended input
filters.
5.2.1.1 Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode. Single-ended oper-
ation is only supported for ADC3. See Section 5.2.2.
5.2.1.2 Software Mode
For single-ended operation on ADC1-ADC3 (AIN1 to AIN6), the ADCx_SINGLE bit in the register “ADC
Control & DAC De-Emphasis (Address 05h)” on page 44 must be set appropriately (see Figure 21 on
page 50 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume
Control (Address 11h-16h)” on page 48. The ADC output data is in 2’s complement binary format. For in-
puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-
spectively, and cause the ADC Overflow bit in the register “Status (Address 19h) (Read Only)” on page 49
to be set to a ‘1’.
DS646F1
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