CS98200 Datasheet, PDF (26/60 Pages) Cirrus Logic – New Highly-Integrated Processor for Tommorrow DVD Players and DVD Receivers

CS98200
Next Generation DVD Processor
4. CS98200 DEVICE SUMMARY
4.1 Block Diagram
The CS98200 block diagram is shown in Figure 20.
RISC0
(Navigation
and Control)
RISC1
(Application)
MPEG2 Video
Decoder
SubPicture
Decoder
PLL ^(Main,
Audio, SDRAM)
PCM, SPDIF
Interface
AUDIO DSP
DMA Control
(BitBlt, CSS)
Graphics
2/4/8/16 Bt it OSD
Video Processor
(I/O, Scale, PIP, Mix)
Host Interface
(ATAPI,AV,ISA)
External IO
(GPIO, IR)
Mem Control
(SDRAM,ROM)
Registers
Figure 20. CS98200 Block Diagram
4.2 CS98200 Device Details
4.2.1 RISC-32 Processors
• Two Powerful 32-bit RISC processors (RISC0
and RISC1), Generation III
• Virtual memory support
• Optimizing C compiler
• Big or little endian data formats support
• MAC multiply/accumulate in 2 cycles with
C support
• 4 Kbyte instruction cache, 2 Kbyte data
cache
• Single cycle instructions, runs at 180 Mhz
4.2.2 Powerful 24/32-Bit DSP
• Powerful 24/32-bit DSP processor
• 24-bit fixed point logic, with 54-bit accumu-
lator
• Single-cycle throughput, 2-cycle latency
multiply accumulate, 32-bit simple integer
logic. 8-Kbyte instruction cache
• Single cycle instructions, runs at 180 Mhz
• Expanded 4 Kbyte X + 16 KByte Y paged
program visible local memory, Total data
RAM = 20 KBytes
4.2.3 System Controls
• Includes several hardware lockable sema-
phore registers
• General-purpose register for inter-processor
communication
• 32-bit timers for I/O and other uses, with
programmable interval rates
• Both hardware and software interrupts on
data or debug
• Built in PLLs generate all required clocks
from 27 Mhz input clock
4.2.4 Memory Controller
• Supports standard SDRAM and SGRAM,
32-bit data mode only, from 4 MByte to 32
MByte
• Includes a separate dedicated DRAM clock,
so memory can run asynchronous to the sys-
tem clock
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Copyright 2002 Cirrus Logic (All Rights Reserved)
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