CS5366_08 Datasheet, PDF (25/41 Pages) Cirrus Logic – 114 dB, 192 kHz, 6-Channel A/D Converter

CS5366
4.7 Master and Slave Clock Frequencies
Tables 4 through 12 show the clock speeds for sample rates of 48 kHz, 96 kHz and 192 kHz. The
MCLK/LRCK ratio should be kept at a constant value during each mode. In Master Mode, the device outputs
the frequencies shown. In Slave Mode, the SCLK/LRCK ratio can be set according to design preference.
However, device performance is guaranteed only when using the ratios shown in the tables.
Control Port Mode only
LJ/I²S MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
÷4
49.152
3.072
1024
64
÷3
36.864
3.072
768
64
SSM Fs = 48 kHz
÷2
24.576
3.072
512
64
÷1.5
18.384
3.072
384
64
÷1
12.288
3.072
256
64
Table 4. Frequencies for 48 kHz Sample Rate using LJ/I²S
LJ/I²S MASTER OR SLAVE
DSM Fs = 96 kHz
MCLK Divider
÷4
÷3
÷2
MCLK (MHz)
49.152
36.864
24.567
SCLK (MHz)
6.144
6.144
6.144
MCLK/LRCK Ratio
512
384
256
SCLK/LRCK Ratio
64
64
64
Table 5. Frequencies for 96 kHz Sample Rate using LJ/I²S
÷1.5
18.384
6.144
192
64
÷1
12.288
6.144
128
64
LJ/I²S MASTER OR SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/LRCK Ratio
SCLK/LRCK Ratio
÷4
49.152
12.288
256
64
÷3
36.864
12.288
192
64
QSM Fs = 192 kHz
÷2
24
12.288
128
64
÷1.5
18.384
12.288
96
64
Table 6. Frequencies for 192 kHz Sample Rate using LJ/I²S
÷1
12.288
12.288
64
64
TDM MASTER
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
÷4
49.152
12.288
1024
256
÷3
36.864
12.288
768
256
SSM Fs = 48 kHz
÷2
24.567
12.288
512
256
Table 7. Frequencies for 48 kHz Sample Rate using TDM
÷1.5
18.384
12.288
384
256
÷1
12.288
12.288
256
256
TDM SLAVE
MCLK Divider
MCLK (MHz)
SCLK (MHz)
MCLK/FS Ratio
SCLK/FS Ratio
DS626F3
SSM Fs = 48 kHz
÷4
÷3
÷2
49.152
36.864
24.567
12.288
12.288
12.288
1024
768
512
256
256
256
Table 8. Frequencies for 48 kHz Sample Rate using TDM
÷1.5
18.384
12.288
384
256
÷1
12.288
12.288
256
256
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