WM8152 Datasheet, PDF (24/28 Pages) Wolfson Microelectronics plc – Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output

WM8152
Production Data
REGISTER MAP DESCRIPTION
The following table describes the function of each of the control bits shown in Table 5.
REGISTER
Setup
Register 1
Setup
Register 2
Setup
Register 3
Software
Reset
Setup
Register 4
BIT
BIT
NO NAME(S)
0
EN
1
CDS
3:2 Reserved
5:4 PGAFS[1:0]
6
MODE3
7
Reserved
1:0 Reserved
2
INVOP
3
VRLCEXT
4
Reserved
5 RLCDACRNG
7:6
DEL[1:0]
3:0 RLCV[3:0]
5:4 CDSREF[1:0]
7:6 Reserved
2:0 Reserved
3
RLCINT
5:4 INTM[1:0]
DEFAULT
1
1
11
00
0
0
11
0
0
0
1
00
1111
01
00
101
0
00
DESCRIPTION
0 = complete power down, 1 = fully active.
Select correlated double sampling mode: 0 = single ended mode,
1 = CDS mode.
Must be set to one
Offsets PGA output to optimise the ADC range for different polarity sensor
output signals. Zero differential PGA input signal gives:
00 = Zero output
(use for bipolar video)
01 = Zero output
10 = Full-scale positive output
(use for negative going video)
11 = Full-scale negative output
(use for positive going video)
Required when operating in MODE3: 0 = other modes, 1 = MODE3.
Must be set to zero
Must be set to one
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
When set powers down the RLCDAC, changing its output to Hi-Z, allowing
VRLC/VBIAS to be externally driven.
Must be set to zero
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to VDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
Sets the output latency in ADC clock periods.
1 ADC clock period = 2 MCLK periods except in Mode 2 where 1 ADC
clock period = 3 MCLK periods.
00 = Minimum latency
01 = Delay by one ADC clock
period
10 = Delay by two ADC clock periods
11 = Delay by three ADC clock
periods
Controls RLCDAC driving VRLC pin to define single ended signal
reference voltage or Reset Level Clamp voltage. See Electrical
Characteristics section for ranges.
CDS mode reset timing adjust.
00 = Advance 1 MCLK period
01 = Normal
10 = Retard 1 MCLK period
11 = Retard 2 MCLK periods
Must be set to zero
Any write to Software Reset causes all cells to be reset.
It is recommended that a software reset be performed after a power-up
before any other register writes.
Must be set to 101
This bit is used to determine whether Reset Level Clamping is enabled.
0 = RLC disabled, 1 = RLC enabled.
Colour selection bits used in internal modes.
00 = Red, 01 = Green, 10 = Blue and 11 = Reserved.
See Table 2 for details.
7:6 Reserved
00
Must be set to zero
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PD, Rev 4.3, August 2008
24