CS8421_10 Datasheet, PDF (23/36 Pages) Cirrus Logic – 32-bit, 192-kHz Asynchronous Sample Rate Converter

CS8421
OLRCK
OSCLK
SDOUT/
TDM_IN
256 OSCLKs
MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB MSB
LSB
SDOUT 4, ch A
SDOUT 4, ch B
SDOUT 3, ch A
SDOUT 3, ch B
SDOUT 2, ch A
SDOUT 2, ch B
SDOUT 1, ch A
SDOUT 1, ch B
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
32 clks
Figure 12. TDM Master Mode Timing Diagram
Output
Clock
Source
LRCK
SCLK
CS8421₁
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
Slave
SDIN
CS8421₂
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
Slave
SDIN
CS8421₃
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
Slave
SDIN
CS8421₄
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
Slave
SDIN
DSP
LRCK
SCLK
SDIN
Slave
OLRCK OSCLK SDOUT
PCM Source 1
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
PCM Source 2
PCM Source 3
PCM Source 4
Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)
CS8421₁
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
Master
SDIN
CS8421₂
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
SDIN
Slave
CS8421₃
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
SDIN
Slave
CS8421₄
OLRCK
OSCLK
TDM_IN
SDOUT
ILRCK
ISCLK
SDIN
Slave
DSP
LRCK
SCLK
SDIN
Slave
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
OLRCK OSCLK SDOUT
PCM Source 1
PCM Source 2
PCM Source 3
PCM Source 4
Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)
4.5 Reset, Power-Down, and Start-Up
When RST is low, the CS8421 enters a low-power mode, all internal states are reset, and the outputs are
disabled. After RST transitions from low to high, the part senses the resistor value on the configuration pins
(MS_SEL, SAIF, and SAOF) and sets the appropriate mode of operation. After the mode has been set (ap-
proximately 4 μs), the part is set to normal operation and all outputs are functional.
DS641F4
23