CS42428 Datasheet, PDF(23/67 Page) Cirrus Logic – 114 dB, 192kHz 8-Ch CODEC WITH PLL

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CS42428 Datasheet, PDF (23/67 Pages) Cirrus Logic – 114 dB, 192kHz 8-Ch CODEC WITH PLL

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CS42428

3.5.4.2 OLM Config #2

This configuration will support up to 8 channels of DAC data, 6 channels of ADC data and will handle up

to 20-bit samples at a sampling frequency of 96 kHz on all channels for both the DAC and ADC. The out-

put data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run

at the DAC Serial Port sample frequency.

Functional Mode Register (addr = 03h)

Set DAC_FMx = 00,01,10

Set ADC_FMx = 00,01,10

Set ADC_CLK_SEL = 1

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00,01,10

Set DAC_OLx bits = 00,01

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 1

Set SAI_SP M/S = 1

Set EXT ADC SCLK = 1

Description

DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK

ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK

Configure ADC_SDOUT to be clocked from the ADC_SP clocks.

Select the digital interface format when not in one line mode

Select ADC operating mode, see table below for valid combinations

Select DAC operating mode, see table below for valid combinations

Set CODEC Serial Port to master mode.

Set Serial Audio Interface Port to master mode.

Identify external ADC clock source as DAC Serial Port.

ADC Mode

Not One

Line Mode

One Line

Mode #1

One Line

Mode #2

Not One Line Mode

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM/QSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=64Fs

DAC_LRCK=SSM/DSM

ADC_SCLK=128Fs

ADC_LRCK=CX_LRCK

DAC_SCLK=64Fs

DAC_LRCK=SSM

ADC_SCLK=256Fs

ADC_LRCK=CX_LRCK

DAC Mode

One Line Mode #1

DAC_SCLK=128Fs

DAC_LRCK=SSM

ADC_SCLK=64Fs

ADC_LRCK=SSM/DSM/QSM

DAC_SCLK=128Fs

DAC_LRCK=SSM

ADC_SCLK=128Fs

ADC_LRCK=CX_LRCK

not valid

One Line Mode #2

not valid

LRCK

SCLK

MCLK

SDOUT1

SDOUT2

C S 53 6 1

CS5361

RMCK

ADCIN1

ADCIN2

ADC_SCLK

ADC_LRCK

AD C_S DO UT

64Fs ,128Fs,

256Fs

ADC Data

MCLK

SCLK_PORT1

L RC K_PO R T1

SD IN _POR T1

DA C_S CL K

DAC_LRCK

DAC_SDIN1

DAC_SDIN2

DAC_SDIN3

DAC_SDIN4

CS42428

64Fs,128Fs

SCLK_PORT2

L RC K_P OR T 2

SDOUT1_PORT2

SDOUT2_PORT2

SDOUT3_PORT2

SDOUT4_PORT2

DIGITAL AUDIO

PROCESSOR

Figure 14. OLM Configuration #2

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