CS61880 Datasheet, PDF (22/70 Pages) Cirrus Logic – OCTAL E1 LINE INTERFACE UNIT

CS61880
4. OPERATION
The CS61880 is a full featured line interface unit
for up to eight E1 75 Ω or E1 120 Ω lines. The de-
vice provides an interface to twisted pair or co-ax-
ial media. A matched impedance technique is
employed that reduces power and eliminates the
need for matching resistors. As a result, the device
can interface directly to the line through a trans-
former without the need for matching resistors on
the transmit side. The receive side uses the same re-
sistor values for all E1 settings.
5. POWER-UP
On power-up, the device is held in a static state un-
til the power supply achieves approximately 70%
of the power supply voltage. Once the power sup-
ply threshold is passed, the analog circuitry is cali-
brated, the control registers are reset to their default
settings, and the various internal state machines are
reset. The reset/calibration process completes in
about 30 ms.
6. MASTER CLOCK
The CS61880 requires a 2.048 MHz reference
clock with a minimum accuracy of ±100 ppm. This
clock may be supplied from internal system timing
or a CMOS crystal oscillator and input to the
MCLK pin.
The receiver uses MCLK as a reference for clock
recovery, jitter attenuation, and the generation of
RCLK during LOS. The transmitter uses MCLK as
the transmit timing reference during a blue alarm
transmit all ones condition. In addition, MCLK
provides the reference timing for wait state genera-
tion.
In systems with a jittered transmit clock, MCLK
should not be tied to the transmit clock, a separate
crystal oscillator should drive the reference clock
input. Any jitter present on the reference clock will
not be filtered by the jitter attenuator and can cause
the CS61880 to operate incorrectly.
7. G.772 MONITORING
The receive path of channel zero of the CS61880
can be used to monitor the receive or transmit paths
of any of the other channels. The signal to be mon-
itored is multiplexed to channel zero through the
G.772 Multiplexer. The multiplexer and channel
zero then form a G.772 compliant digital Protected
Monitoring Point (PMP). When the PMP is connect-
ed to the channel, the attenuation in the signal path is
negligible across the signal band. The signal can be
observed using RPOS, RNEG, and RCLK of chan-
nel zero or by putting channel zero in remote loop-
back, the signal can be observed on TTIP and
TRING of channel zero.
The G.772 monitoring function is available during
both host mode and hardware mode operation. In
host modes, individual channels are selected for
monitoring via the Performance Monitor Regis-
ter (0Bh) (See Section 14.12 on page 36)). In hard-
ware mode, individual channels are selected
through the A3:A0 pins (Refer to Table 6 below for
address settings).
Table 6. G.772 Address Selection
Address [A3:A0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Channel Selection
Monitoring Disabled
Receiver Channel # 1
Receiver Channel # 2
Receiver Channel # 3
Receiver Channel # 4
Receiver Channel # 5
Receiver Channel # 6
Receiver Channel # 7
Monitoring Disabled
Transmitter Channel # 1
Transmitter Channel # 2
Transmitter Channel # 3
Transmitter Channel # 4
Transmitter Channel # 5
Transmitter Channel # 6
Transmitter Channel # 7
NOTE: In hardware mode the A4 pin must be tied low
at all times.
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DS450PP3