CS5566 Datasheet, PDF (22/30 Pages) Cirrus Logic – ±2.5 V / 5 V, 5 kSps, 24-bit ΔΣ ADC

3/25/08
CS5566
Figure 16 illustrates the device with a small signal 1/1,000,000 of full scale. The signal input for figure 15
is about 8.2 microvolts peak to peak, or about 17 codes peak to peak. Figure 17 illustrates the converter
with a signal at about 2.6 microvolts peak to peak, or about 5 codes peak to peak. The CS5566 achieves
superb performance with this small signal.
Figure 18 illustrates the noise floor of the converter from 0.1 Hz to 2.5 kHz. The plot is entirely free of spu-
rious frequency content due to digital activity inside the chip.
Figure 19 illustrates a noise histogram of the converter constructed from 4096 samples.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
0
277 Hz, -130 dB
32k Samples @ 5 kSps
500
1k
1.5k
2k
2.5k
Frequency (Hz)
Figure 17. Spectral Performance, -130 dB
-60
-80
-100
Shorted Input
2M Samples @ 5 kSps
16 Averages
-120
-140
-160
-180
0.1
1
10
100
1k
2.5k
Frequency (Hz)
Figure 18. Spectral Plot of Noise with Shorted Input
100
90
4096 Samples
80
Mean = 96.32
Std. Dev. = 21.3
70
Max - Min = 150
60
50
40
30
20
10
0
Output Codes
Figure 19. Noise Histogram (4096 Samples)
22
DS806PP1