CS5529 Datasheet, PDF (21/30 Pages) Cirrus Logic – 16 BIT PROGRAMMABLE ADC WITH 6 BIT LATCH

CS5529
Performing Conversions
The CS5529 offers two modes of performing con-
versions: single conversion and continuous conver-
sions. The sections that follow detail the
differences and provides examples illustrating how
to use the modes. Note that it is assumed that the
configuration register has been initialized before
conversions are performed.
Performing Conversions with PF bit = 0
A single conversion is performed after the user
transmits the single conversion command (0xC0
Hexadecimal). At the completion of the conver-
sion, the DF (Done Flag) bit of the configuration
register will be set to a logic 1. While the conver-
sion is being performed, the user can read the con-
figuration register to determine if the DF bit is set.
Once DF has been set, the read conversion data reg-
ister command (0x96 Hexadecimal) can be issued
to read the conversion data register to obtain the
conversion data word.
Note:
1)The DF bit of the configuration register will
be cleared to logic 0 when the conversion
data register, the gain register, or the offset
register is read. Reading only the
configuration register will not clear the DF flag
bit. 2) If another single conversion command
is issued to the converter while it is
performing a conversion, the filter will
abandon the current conversion and restart a
new convolution cycle.
Performing Conversions with PF bit = 1
The PF (Port Flag) bit in the configuration register
eliminates the need for the user to monitor the DF
(Done Flag) in the configuration register to deter-
mine if the conversion is available. When PF is set
to a logic 1, SDO’s output pin behaves as a flag sig-
nal indicating when conversions are completed.
SDO will fall to logic 0 once a new conversion is
complete.
Single Conversion
A single conversion is performed after the user
transmits the single conversion command (0xC0
Hexadecimal). At the completion of the conver-
sion, SDO will fall to logic 0 to indicate that the
conversion is complete. To acquire the conversion,
the user must issue 8 SCLKs with SDI = logic 0
(i.e. the NULL command) to clear the SDO flag.
Upon the falling edge of the 8th SCLK, the SDO
pin will present the first bit (MSB) of the conver-
sion word. 24 SCLKs (high, then low) are then re-
quired to read the conversion word from the port.
Note:
1) The user must not give an explicit
command (other than the NULL command) to
read the conversion data register when the
PF bit is set to logic 1. 2) The data conversion
word must be read before a new command
can be entered as the converter will remain in
the data mode until the conversion word is
read. 3) Once the conversion is read the
converter returns to the command mode.
Continuous Conversions
Continuous conversions are performed after the
user transmits the continuous conversions com-
mand (0xA0 Hexadecimal). At the completion of a
conversion, SDO will fall to logic 0 to indicate that
the conversion is complete. To read the conversion
word, the user must issue 8 SCLKs with SDI = log-
ic 0 (i.e. the NULL command) to clear the SDO
flag. Upon the falling edge of the 8th SCLK, the
SDO pin will present the first bit (MSB) of the con-
version word. 24 SCLKs (high, then low) are then
required to read the conversion word from the port.
When operating in the continuous conversion
mode, the user need not read every conversion. If
the user chooses not to read a conversion after SDO
falls, SDO will rise one XIN clock cycle before the
next conversion word is available and then fall
again to signal that another conversion word is
available. To exit the continuous conversion mode,
the user must issue any valid command, other than
the NULL command, to the SDI input when the
SDO flag falls. For instance, the user can just read
DS246F1
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