CS4812 Datasheet, PDF (21/36 Pages) Cirrus Logic – Fixed Function Multi-Effects Audio Processor

CS4812
and a memory address pointer (MAP) byte. The
MAP byte contains the address of the control port
register to be accessed. Following the preamble,
the host controller sends the actual data byte to be
written to the register designated by the MAP. The
host controller then de-asserts CS. Figure 16 shows
the SPI slave mode write flow diagram.
SET CS LOW
WRITE ADDRESS BYTE
WITH R/W BIT = 0
WRITE MAP BYTE
WRITE DATA BYTE
Y
MORE DATA?
N
SET CS HIGH
Figure 16. SPI Slave Write Flow Diagram
In SPI slave mode, a read sequence from an exter-
nal controller is shown in Figure 17. The host con-
troller executes a partial write-cycle by sending a
16-bit write preamble to the CS4812 with the MAP
byte set to the address of the control port byte reg-
ister to be read. The host controller then de-asserts
CS, re-asserts CS, and sends the 7-bit chip address
followed by the R/W bit set to 1. The host control-
ler then clocks out the control port register desig-
nated by the MAP byte. The host controller then
de-asserts CS. Figure 18 shows the SPI mode slave
read flow diagram initiated by the host microcon-
troller. Figure 19 shows the SPI slave mode read
flow diagram incorporating the DSP REQ signal.
REQ is used to notify the host controller that a data
byte from the DSP is waiting to be read.
The behavior of the REQ signal is dependent on
when data is written to the serial control port output
register in relation to CCLK and bit 2 of the current
byte being transferred. There are three cases of
REQ behavior:
1. The REQ line will be de-asserted immediately
following the rising edge of CCLK on the D2 bit of
the current byte being transferred if there is no data
in the serial control port output register. The REQ
line remains de-asserted and a stop condition
CS
(input)
CLK
(input)
CDIN
(input)
CDOUT
(output)
REQ
(output)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CHIP ADDRESS (WRITE)
MAP BYTE
CHIP ADDRESS (READ)
0 0 1 0 0 0 0 0 INCR 6 5 4 3 2 1 0
MSB
R/W
0 0 1 0 0 0 01
R/W
DATA
7 6 5 4 3 210
DATA
7 6 5 4 3 210
Figure 17. Control Port Timing, SPI Slave Mode Read
DS291PP3
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