CS4223_03 Datasheet, PDF (20/34 Pages) Cirrus Logic – 24-Bit 105 dB Audio Codec with Volume Control

6. PIN DESCRIPTIONS — CS4223
NC
XTO
XTI
LRCK
SCLK
VD
DGND
SDOUT
SDIN
DIF1
DIF0
DEM0
VL
NC
CS4223
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
NC
RST
AOUTL-
AOUTL+
AOUTR+
AOUTR-
AGND
VA
AINL+
AINL-
DEM1
AINR+
AINR-
NC
CS4223 CS4224
NC
XTI, XTO
LRCK
SCLK
VD
DGND
SDOUT
1,14,15, 28 No Connect - These pins are not connected internally and should be tied to DGND to mini-
mize noise coupling.
2,3
Crystal Connections (Input/Output) - Input and output connections for the crystal used to
clock the CS4223. Alternatively, a clock may be input into XTI. This is the clock source for the
delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x,
or 512x Fs in Slave Mode and 256x in Master Mode.
Fs (kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
XTI (MHz)
384x
12.2880
16.9344
18.4320
Table 2. Common Clock Frequencies
512x
16.3840
22.5792
24.5760
4
Left/Right Clock (Input) - Determines which channel is currently being input/output of the
serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the
input sample rate. Although the outputs for each ADC channel are transmitted at different
times, Left/Right pairs represent simultaneously sampled analog inputs. The required relation-
ship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The
options are detailed in Figures 8 - 11.
5
Serial Data Clock (Input) - Clocks the individual bits of the serial data into the SDIN pin and
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and
serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11.
6
Digital Power (Input) - Positive power supply for the digital section. Typically 5.0 VDC.
7
Digital Ground (Input) - Digital ground for the digital section.
8
Serial Data Output (Output) - Two's complement MSB-first serial data is output on this pin.
The required relationship between the left/right clock, serial clock and serial data is defined by
the DIF1-0 pins. The options are detailed in Figures 8 - 11.
20
DS290F1