PB50 Datasheet, PDF (2/5 Pages) Cirrus Logic – POWER BOOSTER AMPLIFIER

PB50
Product Innova tionFrom
ABSOLUTE MAXIMUM RATINGS
SUPPLY VOLTAGE, +V_S to –V_S
OUTPUT CURRENT, within SOA
POWER DISSIPATION, internal at T_C = 25°C¹
INPUT VOLTAGE, referred to common
TEMPERATURE, pin solder—10 sec max
TEMPERATURE, junction¹
TEMPERATURE, storage
OPERATING TEMPERATURE RANGE, case
SPECIFICATIONS
PARAMETER
INPUT
OFFSET VOLTAGE, initial
OFFSET VOLTAGE, vs. temperature
INPUT IMPEDANCE, DC
INPUT CAPACITANCE
CLOSED LOOP GAIN RANGE
GAIN ACCURACY, internal Rg, Rf
GAIN ACCURACY, external Rf
PHASE SHIFT
OUTPUT
VOLTAGE SWING
VOLTAGE SWING
VOLTAGE SWING
CURRENT, continuous
SLEW RATE
CAPACITIVE LOAD
SETTLING TIME to .1%
POWER BANDWIDTH
SMALL SIGNAL BANDWIDTH
SMALL SIGNAL BANDWIDTH
POWER SUPPLY
VOLTAGE, ±V_S3
CURRENT, quiescent
THERMAL
RESISTANCE, AC junction to case⁴
RESISTANCE, DC junction to case
RESISTANCE, junction to air
TEMPERATURE RANGE, case
TEST CONDITIONS²
Full temperature range
A_V = 3
A_V = 10
F = 10kHz, AV_CL = 10, C_C = 22pF
F = 200kHz, AV_CL = 10, C_C = 22pF
Io = 2A
Io = 1A
Io = .1A
Full temperature range
Full temperature range
R_L = 100Ω, 2V step
V_C = 100Vpp
C_C = 22pF, A_V = 25, Vcc = ±100
C_C = 22pF, A_V = 3, Vcc = ±30
Full temperature range
V_S = ±30
V_S = ±60
V_S = ±100
Full temp. range, F > 60Hz
Full temp. range, F < 60Hz
Full temperature range
Meets full range specifications
MIN
25
3
V_S–11
V_S–10
V_S–8
2
50
160
±30⁵
–25
TYP
±.75
–4.5
50
3
10
±10
±15
10
60
V_S –9
V_S –7
V_S –5
100
2200
2
320
100
1
±60
9
12
17
1.8
3.2
30
25
200V
2A
35W
±15V
300°C
150°C
–65 to +150°C
–55 to +125°C
MAX
±1.75
–7
25
±15
±25
±100
12
18
25
2.0
3.5
85
UNITS
V
mV/°C
kΩ
pF
V/V
%
%
°
°
V
V
V
A
V/µs
pF
µs
kHz
kHz
MHz
V
mA
mA
mA
°C/W
°C/W
°C/W
°C
NOTES: 1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation to
achieve high MTTF (Mean Time to Failure).
2. The power supply voltage specified under typical (TYP) applies, T_C = 25°C unless otherwise noted.
3. +V_S and –V_S denote the positive and negative supply rail respectively.
4. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz.
5. +V_S must be at least 15V above COM, –V_S must be at least 30V below COM.
  CAUTION
The PB50 is constructed from MOSFET transistors. ESD handling procedures must be observed.
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
subject to temperatures in excess of 850°C to avoid generating toxic fumes.
2
PB50U