CS1600 Datasheet, PDF (2/18 Pages) Cirrus Logic – Low-cost PFC Controller for Electronic Ballasts

CS1600
1. PIN DESCRIPTIONS
NC 1
STBY 2
IAC 3
FB 4
8 NC
7 VDD
6 GD
5 GND
Pin Name Pin #
I/O
NC
1, 8
-
STBY
2
IN
IAC
3
IN
FB
GND
GD
VDD
4
IN
5
–
6
OUT
7
IN
Table 1. Pin Descriptions
Description
No Connect — Connect these pins to V_DD to prevent any leakage path that could
arise from leaving them unterminated.
Standby — This is an active-low pin. Shorting this pin to GND disables PFC switch-
ing. The input has a pull-up resistor and should be driven with an open-collector
device. Leave this pin unterminated when not in use.
Rectified Line Voltage Sense — The IAC pin is used to sense the rectified line volt-
age. This signal, in conjunction with the signal on the FB pin, is used in the Power
Factor Correction (PFC) algorithm
A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide
noise immunity.
Feedback Voltage Sense — The FB pin is used to sense the output voltage of the
PFC stage. This signal, in conjunction with the signal on the IAC pin, is used in the
Power Factor Correction (PFC) algorithm.
A filter capacitor of up to 2.2 nF may be added between this pin and VDD to provide
noise immunity.
Ground — GND is a common reference for all the functional blocks in this device.
Gate Drive — GD is the output of the device with a source capability of 0.5 A and a
current sink capacity of 1 A.
IC Supply Voltage — V_DD is the input used to provide bias to the device. This pin
has an internal shunt to ground. An external bias needs to be applied for steady-
state operation. A low-ESR ceramic decoupling capacitor at this pin is recommended
for reliable operation of this device.
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DS904A5