CDB61884 Datasheet, PDF (18/22 Pages) Cirrus Logic – Octal T1/E1/J1 Line Interface Evaluation Board

CDB61884
6. BOARD CONFIGURATIONS
6.1 E1 75 Ω Mode Setup
Table 4 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation
board to operate in E1 75 Ω Hardware, Serial Host and Parallel Host operational modes. Before selecting
Host mode, the switches in Table 4 in bold should be set to the position stated.
Table 4. E1 75 Ω Operational Mode Switch/Jumper Position
Switches/Jumpers
S15 (MODE)
S1 (0)
S2 (1)
S3 (2)
S4 (3)
S5 (4)
S6 (5)
S7 (6)
S8 (7)
S9 #1 (MOT_\INTL)
S9 #2 (MUX)
S9 #3 (A4)
S9 #4 (A3)
S9 #5 (A2)
S9 #6 (A1)
S9 #7 (A0)
S10 (JASEL)
S11 (CBLSEL)
S12 (LEN 2)
S13 (LEN 1)
S14 (LEN 0)
J13 (VLOGIC)
J1 (MCLK)
J93 (CLKE)
J23 (TXOE)
Hardware
HARDWARE
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
LOOP FUNCTION
HIGH
LOW (Note 4)
LOW (Note 5)
LOW (Note 5)
LOW (Note 5)
LOW (Note 5)
LOW (Note 5)
ANY POSITION
HIGH (Note 6)
LOW
LOW
LOW
3V
OSCILLATOR
OPEN
OPEN
Serial Host (Note 3)
SERIAL HOST
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
OPEN
NC
OPEN
OPEN
OPEN
3V
OSCILLATOR
OPEN
OPEN
Parallel Host (Note 3)
PARALLEL HOST
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
MOTOROLA/INTEL
MUX/NON-MUX
HIGH
HIGH
HIGH
HIGH
HIGH
OPEN
NC
OPEN
OPEN
OPEN
3V
OSCILLATOR
OPEN
OPEN
3. Connect a standard 25-pin male to female parallel port cable to connector J12 and the control PC.
4. Set “HIGH” to enable BITS Clock Recovery function for only Channel #0 in Hardware Mode.
5. Other settings may be used to enter G.772 Non-Intrusive Monitoring in Hardware Mode. Refer to the
CS61884 Data Sheet for other settings.
6. Set “LOW” to disable receiver Internal line impedance matching function. The external resistors for all
eight receivers must be changed to 9.31 Ω to properly match the input line impedance.
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DS485DB1