CS497014 Datasheet, PDF (17/31 Pages) Cirrus Logic – High Definition Audio Decoder DSP Family with Dual 32-bit Engine Technology

CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
Parameter
Symbol Min
Typical
Max Unit
Delay between PCP_RD then PCP_CS low or PCP_CS then
t_icdr
0
—
— ns
PCP_RD low
Data valid after PCP_CS and PCP_RD low
t_idd
—
—
18 ns
PCP_CS and PCP_RD low for read
t_irpw 24
—
— ns
Data hold time after PCP_CS or PCP_RD high
t_idhr
8
—
— ns
Data high-Z after PCP_CS or PCP_RD high
t_idis
—
—
18 ns
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
t_ird
30
—
— ns
read¹
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
t_irdtw 30
—
— ns
write¹
PCP_RD rising to PCP_IRQ rising
t_irdirqhl —
—
12 ns
Write
Delay between PCP_WR then PCP_CS low or PCP_CS then
t_icdw
0
—
— ns
PCP_WR low
Data setup before PCP_CS or PCP_WR high
t_idsu
8
—
— ns
PCP_CS and PCP_WR low for write
t_iwpw 24
—
— ns
Data hold after PCP_CS or PCP_WR high
t_idhw
8
—
— ns
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
t_iwtrd 30
—
— ns
read¹
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
t_iwd
30
—
— ns
write¹
PCP_WR rising to PCP_BSY falling
t_iwrbsyl —
2*DCLKP + 20
—
ns
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware
application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent overflowing the input data buffer.
CS4953x4/CS4970x4 System Designer’s Guide should be consulted for the firmware speed limitations.
PCP_A[3:0]
PCP_D[7:0]
PCP_CS#
PCP_WR#
PCP_RD#
PCP_IRQ#
t iah
LSP
t ias
t idhr
t idd
t icdr
t idis
t irpw
t ird
MSP
t irdtw
t_irdirqh
Figure 7. Parallel Control Port - Intel^ Slave Mode Read Cycle
DS752F1
17