CS4340A_05 Datasheet, PDF (17/21 Pages) Cirrus Logic – 24-Bit, 192 kHz Stereo DAC for Audio

CS4340A
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
(Note 6)
LRCK Duty Cycle
SCLK Frequency
Parameters
Symbol
Single-Speed Mode Fs
Double-Speed Mode _Fs
Quad-Speed Mode _Fs
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Min
1.024
45
4
84
170
40
-
-
-
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
SCLK rising to MCLK edge delay (Note 7)
t_sclkl
20
t_sclkh
20
t_slrd
20
t_slrs
20
t_sdlrs
20
t_sdh
20
t_smd
8
Notes: 6. Speed mode is detected automatically, based on the input sample rate.
7. Only required for Quad-Speed Mode.
Max
38.4
55
50
100
200
60
128xFs
64xFs
M_------C_-----L_----K_--
2
-
-
-
-
-
-
-
Units
MHz
%
kHz
kHz
kHz
%
Hz
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
MCLK
LRCK
SCLK
SDATA
t _smd
t _slrd
t _slrs
t _sclkh
t _sclkl
t _sdlrs
t _sdh
Figure 17. Serial Input Timing
DS590F2
17