CS5101A Datasheet, PDF (16/40 Pages) Cirrus Logic – 16-Bit, 100kHz/ 20kHz A/D Converters

CS5101A CS5102A
MODE
PDT
RBT
SSC
FRN
SCKMOD
1
1
0
0
OUTMOD
1
0
1
0
SCLK
Input
Input
Output
Output
CH1/2
Input
Input
Input
Output
HOLD
Input
Input
Input
X
Table 2. Serial Output Modes
Output Mode Control
The CS5101A and CS5102A can be configured
in three different output modes, as well as an in-
ternal, synchronous loop-back mode. This allows
great flexibility for design into a wide variety of
systems. The operating mode is selected by set-
ting the states of the SCKMOD and OUTMOD
pins. In all modes, data is output on SDATA,
starting with the MSB. Each subsequent data bit
is updated on the falling edge of SCLK.
When SCKMOD is high, SCLK is an input, al-
lowing the data to be clocked out with an
external serial clock at rates up to 5 MHz. Addi-
tional clock edges after #16 will clock out logic
’1’s on SDATA. Tying SCKMOD low reconfig-
ures SCLK as an output, and the converter clocks
out each bit as it’s determined during the conver-
sion process, at a rate of 1/4 the master clock
speed. Table 2 shows an overview of the different
states of SCKMOD and OUTMOD, and the cor-
responding output modes.
Pipelined Data Transmission (PDT)
PDT mode is selected by tying both SCKMOD
and OUTMOD high. In PDT mode, the SCLK
pin is an input. Data is registered during conver-
sion, and output during the following conversion
cycle. HOLD must be brought low, initiating an-
other conversion, before data from the previous
conversion is available on SDATA. If all the data
has not been clocked out before the next falling
edge of HOLD, the old data will be lost
(Figure 3).
0
4
8
60 64 68 72 76
CLKIN (i)
HOLD (i)
CH1/2 (i)
Internal
Status
Converting Ch. 2
Tracking Ch. 1
SCLK (i)
SDATA (o) D15 D14
D1 D0 (Ch. 1)
SSH/SDL (o)
TRK1 (o)
TRK2 (o)
0
4
8
60 64 68 72 76
Converting Ch. 1
Tracking Ch. 2
D15 D14
D1 D0 (Ch. 2)
0
D15
Figure 3. Pipelined Data Transmission Mode (PDT)
16
DS45F2