CS4344_05 Datasheet, PDF (16/24 Pages) Cirrus Logic – 10-PIN, 24-BIT, 192KHz STEREO D/A CONVERTER

CS4344/5/6/8
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN
for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always
be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the
DAC output automatically goes to it’s zero data state.
USER: Apply Power
VQ and outputs
ramp down
Power-Down State
VQ and outputs low
VQ and outputs
ramp down
USER: Remove
MCLK
USER: Apply MCLK
VQ and outputs ramp up
USER: Remove
MCLK
USER: Remove
LRCK
USER: change
MCLK/LRCK ratio
W ait State
USER: Apply LRCK
MCLK/LRCK Ratio Detection
USER: Remove
LRCK
USER: change
MCLK/LRCK ratio
USER: No SCLK
SCLK mode = internal
Normal Operation
D e -e m p h a sis
available
USER: Applied SCLK
SCLK mode = external
Normal Operation
D e -e m p h a sis
not available
Analog Output
is Generated
Analog Output
is Generated
Figure 12. CS4344/5/6/8 Initialization and Power-down Sequence
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