CS4340 Datasheet, PDF (16/28 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC for Audio

CS4340
4. APPLICATIONS
4.1 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4340
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 4 shows the recommended power arrange-
ment with VA connected to a clean supply. Decou-
pling capacitors should be located as close to the
device package as possible.
4.2 Oversampling Modes
The CS4340 operates in one of two oversampling
modes. Base Rate Mode supports input sample
rates up to 50 kHz while High Rate Mode supports
input sample rates up to 100 kHz. The devices op-
erate in Base Rate Mode (BRM) when
MCLK/LRCK is 256, 384 or 512 and in High Rate
Mode (HRM) when MCLK/LRCK is 128 or 192.
4.3 Recommended Power-up Sequence
RST should be held low until the power supply,
master and left/right clocks are stable.
4.4 Popguard^® Transient Control
The CS4340 uses Popguard^® technology to mini-
mize the effects of output transients during power-
up and power-down. This technique, when used
with external DC-blocking capacitors in series with
the audio outputs, minimizes the audio transients
commonly produced by single-ended single-supply
converters.
When the device is initially powered-up, the audio
outputs, AOUTL and AOUTR, are clamped to
AGND. Following a delay of approximately 1000
sample periods, each output begins to ramp toward
the quiescent voltage. Approximately 10,000
left/right clock cycles later, the outputs reach V_Q
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to the quiescent voltage, mini-
mizing the power-up transient.
To prevent transients at power-down, the device
must first enter its power-down state by setting the
RST pin low. When this occurs, audio output ceas-
es and the internal output buffers are disconnected
from AOUTL and AOUTR. In their place, a soft-
start current sink is substituted which allows the
DC-blocking capacitors to slowly discharge. Once
this charge is dissipated, the power to the device
may be turned off and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
it is necessary to ensure that the DC-blocking ca-
pacitors have fully discharged before turning off
the power or exiting the power-down state. If not, a
transient will occur when the audio outputs are ini-
tially clamped to AGND. The time that the device
must remain in the power-down state is related to
the value of the DC-blocking capacitance. For ex-
ample, with a 3.3 µF capacitor, the minimum pow-
er-down time will be approximately 0.4 seconds.
Use of the Mute Control function is recommended
for designs requiring the absolute minimum in ex-
traneous clicks and pops. Also, use of the Mute
Control function can enable the system designer to
achieve idle channel noise/signal-to-noise ratios
which are only limited by the external mute circuit.
See the CDB4340/41 data sheet for a suggested
mute circuit.
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