CS4953XX Datasheet, PDF (15/38 Pages) Cirrus Logic – 32-bit Audio Decoder DSP Family with Dual DSP Engine Technology

CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.11 Switching Characteristics — Serial Control Port - SPI Master Mode
Parameter
SCP_CLK frequency¹
SCP_CS# falling to SCP_CLK rising ³
Symbol
f_spisck
t_spicss
Min
-
-
Typical
11*DCLKP +
(SCP_CLK PERIOD)/2
Max
F_xtal/2²
-
Units
MHz
ns
SCP_CLK low time
t_spickl
18
-
ns
SCP_CLK high time
t_spickh
18
-
ns
Setup time SCP_MISO input
t_spidsu
11
-
ns
Hold time SCP_MISO input
t_spidh
5
-
ns
SCP_CLK low to SCP_MOSI output valid
t_spidov
-
11
ns
SCP_CLK low to SCP_CS# falling
t_spicsl
7
-
ns
SCP_CLK low to SCP_CS# rising
t_spicsh
-
11*DCLKP +
(SCP_CLK PERIOD)/2
-
ns
Bus free time between active SCP_CS#
SCP_CLK falling to SCP_MOSI output high-Z
t_spicsx
t_spidz
-
3*DCLKP
-
ns
20
ns
1. The specification f_spisck indicates the maximum speed of the hardware. The system designer should be aware that
Y _{the actual maximum speed of the communication port may be limited by the firmware application.}
2. See Section 5.8.
3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a
R _{tested parameter}
.
INA ^tspicss
EE_CS#
t_spicsl
t_spickl
0
1
2
6
7
0
5
IM ^SCP_CLK
f_spisck
t_spickh
L _{SCP_MISO}
E _{SCP_MOSI}
A6
t_spidsu
A5
t_spidh
A0 R/W MSB
t_spidov
MSB
t_spicsx
6
7
t_spicsh
LSB
LSB
t_spidz
PR ^{Figure 4. Serial Control Port - SPI Master Mode Timing}
DS705PP2
®Copyright 2008 Cirrus Logic, Inc.
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