CS4334_08 Datasheet, PDF (15/24 Pages) Cirrus Logic – 8-Pin, 24-Bit, 96 kHz Stereo D/A Converter

Confidential Draft
3/11/08
CS4334/5/8/9
down state is related to the value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the
time that the device must remain in the power-down state will be approximately 0.4 seconds.
4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4334 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangement
with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located
as close to the device package as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 15 - 22.
LRCK
Left Channel
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4 +5 +4 +3 +2 +1 LSB
Internal SCLK Mode
I²S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I²S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
I²S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I²S)
LRCK
SCLK
SDATA
Left Channel
M SB -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 LS B
Right Channel
M SB -1 -2 -3 -4 +5 +4 +3 +2 +1 LS B
Internal SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
External SCLK Mode
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
DS248F5
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