CS5560_09 Datasheet, PDF (13/32 Pages) Cirrus Logic – ±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC

5/4/09
CS5560
2. OVERVIEW
The CS5560 is a 24-bit analog-to-digital converter capable of 50 kSps conversion rate. The device is ca-
pable of switching multiple input channels at a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed for fast settling and settles to full accuracy in
one conversion.
The converter is a serial output device. The serial port can be configured to function as either a master or
a slave.
The converter can operate from an analog supply of 5V or from ±2.5V. The digital interface supports stan-
dard logic operating from 1.8, 2.5, or 3.3 V.
The CS5560 converts at 50 kSps when operating from a 16 MHz input clock.
3. THEORY OF OPERATION
The converter should be reset after the power supplies and voltage reference are stable.
The CS5560 converter provides high-performance measurement of DC or AC signals. The converter can
be used to perform single conversions or continuous conversions upon command. Each conversion is in-
dependent of previous conversions and can settle to full specified accuracy, even with a full-scale input
voltage step. This is due to the converter architecture which uses a combination of a high-speed delta-sig-
ma modulator and a low-latency filter architecture.
Once power is established to the converter, a reset must be performed. A reset initializes the internal con-
verter logic.
If CONV is held low, the converter will convert continuously with RDY falling every 320 MCLKs. This is
equivalent to 50 kSps if MCLK = 16.0 MHz. If CONV is tied to RDY, a conversion will occur every 322
MCLKs. If CONV is operated asynchronously to MCLK, it may take up to 324 MCLKs from CONV falling
to RDY falling.
Multiple converters can operate synchronously if they are driven by the same MCLK source and CONV
to each converter falls on the same MCLK falling edge. Alternately, CONV can be held low and all devices
can be synchronized if they are reset with RST rising on the same falling edge of MCLK.
The output coding of the conversion word is a function of the BP/UP pin.
The active-low SLEEP signal causes the device to enter a low-power state. When exiting sleep, the con-
verter will take 3083 MCLK cycles before conversions can be performed. RST should remain inactive
(high) when SLEEP is asserted (low).
3.1 Converter Operation
The CS5560 converts at 50 kSps when synchronously operated (CONV = VLR) from a 16.0 MHz master
clock. Conversion is initiated by taking CONV low. A conversion lasts 320 master clock cycles, but if
CONV is asynchronous to MCLK there may be an uncertainty of 0-4 MCLK cycles after CONV falls to
when a conversion actually begins. This may extend the throughput to 324 MCLKs
When the conversion is completed, the output word is placed into the serial port and RDY goes low. To
convert continuously, CONV should be held low. In continuous conversion mode with CONV held low, a
conversion is performed in 320 MCLK cycles. Alternately RDY can be tied to CONV and a conversion will
occur every 322 MCLK cycles.
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