CS5180 Datasheet, PDF (13/28 Pages) Cirrus Logic – Modulator & 8 kHz to 400 kHz 16-Bit ADC

CS5180
Instability Indicator
The MFLAG signal is functional in both modes of
operation of the part and indicates when the modu-
lator has been overdriven into an unstable condi-
tion. In the modulator only mode (MODE = 0), the
MFLAG signal will remain set for 3 MCLK cycles
when the modulator goes unstable, before being re-
turned to the reset state. While the input condition
causing modulator instability persists, the MFLAG
signal will continually get set for 3 MCLK cycles
and then get reset.
When the decimation filter on the part is operation-
al (MODE = 1), the MFLAG signal is set when the
modulator goes unstable. In this mode, however,
the MFLAG signal stays set until 5,120 MCLK cy-
cles after the input condition causing modulator in-
stability is removed. This delay is provided to
allow the digital filter time to settle, and the part
will output fully settled conversion words after the
MFLAG signal goes low.
Digital Filter Characteristics
Figure 9 illustrates the magnitude versus frequency
plot of the converter when operating at 400 kHz
output word rate. The filter is a non-aliasing 4265
tap filter with a -3 dB corner at 0.4495 of the output
word rate and an out-of-band attenuation of at least
90 dB at frequencies above one half the output
word rate. The passband ripple is less than
±0.05 dB up to the -3 dB corner frequency.
Figure 10 illustrates the phase response of the dig-
ital filter with the converter operating at 400 kHz
output word rate. The filter characteristics change
proportional to changes in the MCLK rate.
The group delay of the digital filter is 2,370 MCLK
cycles (92.6 µs with MCLK = 25.6 MHz), and the
settling time is 4,740 MCLK cycles (185.2 µs).
Serial Interface
The CS5180 has a serial interface through which
conversion words are output in a synchronous self-
clocking format. The serial port consists of the Se-
Figure 9. CS5180 Digital Filter Magnitude Response
(MCLK = 25.6 MHz)
Figure 10. CS5180 Digital Filter Phase Response
(MCLK = 25.6 MHz)
rial Data Output pin (SDO), and its complement
(SDO); Serial Clock (SCLK), and its complement
(SCLK); and the Frame Sync Output (FSO). FSO
falls at the beginning of an output word. Data is
output in twos complement format, MSB first.
FSO stays low for 16 SCLK cycles. SCLK is out-
put at a rate equal to MCLK/3.
Power Supplies / Board Layout
The CS5180 can be operated with VA+ supplies at
5 V and VD+ supplies at 5 V; or with VA+ at 5 V
and VD+ at 3 V.
Figure illustrates the system connection diagram
for the chip. For best performance, each of the
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