CS43122 Datasheet, PDF (13/28 Pages) Cirrus Logic – 122dB, 24-Bit, 192kHz DAC for Digital Audio

CS43122
3. REGISTER DESCRIPTION
3.1 MODE CONTROL REGISTER (ADDRESS 01H)
7
6
5
4
3
2
1
0
CAL
MUTE
M4
M3
M2
M1
M0
PDN
0
0
0
0
0
0
0
0
4.11 Differential DC offset calibration (CAL)
Default = 0
0 - Disabled
1 - Enabled
Function:
Enabling this function will initiate a calibration to minimize the differential DC offset. This function will
be automatically reset following completion of the calibration sequence.
4.12 Soft Mute (MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock
cycles in Operational Mode 0, 2304 cycles in Operational Mode 1 and 4608 cycles in Operational
Mode 2 . The bias voltage on the outputs will be retained and MUTEC will go low at the completion
of the ramp period.
The analog outputs will ramp to a normal state when this function transitions from the enabled to dis-
abled state. The ramp requires 1152 left/right clock cycles in Operational Mode 0, 2304 cycles in Op-
erational Mode 1 and 4608 cycles in Operational Mode 2 . The MUTEC will go high immediately on
disabling of MUTE.
4.13 Mode Select (M4-M0)
Default = 00000
Function:
The Mode Select pins determine the operational mode of the device as detailed in Tables 4-7. The options
include:
Selection of the Digital Interface Format which determines the required relationship between the
Left/Right clock, serial clock and serial data as detailed in Figures 20-23
Selection of the standard 15 µs/50 µs digital de-emphasis filter response, Figure 28, which requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample rates.
Selection of the appropriate operational clocking mode to match the input sample rates.
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