CL-PD6833 Datasheet, PDF (123/216 Pages) Cirrus Logic – PCI-to-CardBus Host Adapter

CL-PD6833
PCI-to-CardBus Host Adapter
10.1.5 Gen Map 0–6 Offset Address Low (I/O)
Register Name: Gen Map 0–6 Offset Address Low (I/O)
I/O Index: 14h, 1Ch, 24h, 2Ch, 34h, 36h, 38h
Memory Offset: 814h, 81Ch, 824h, 82Ch, 834h, 836h, 838h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Offset Address 7:1 (I/O)
Register Per: socket
Register Compatibility Type: ext.
Bit 2
Bit 1
Bit 0
0^a
R/W:0000000
a _{This bit must be programmed to ‘0’ for I/O offset.}
R/W:0
There are seven separate Gen Map Offset Address Low registers, each with identical fields. These
registers are located at the following indexes:
I/O Index
14h
1Ch
24h
2Ch
34h
36h
38h
Memory Offset
814h
81Ch
824h
82Ch
834h
836h
838h
Gen Map Offset Address Low
Gen Map 0 Offset Address Low
Gen Map 1 Offset Address Low
Gen Map 2 Offset Address Low
Gen Map 3 Offset Address Low
Gen Map 4 Offset Address Low
Gen Map 5 Offset Address Low
Gen Map 6 Offset Address Low
Default Operation
Memory Window 0
Memory Window 1
Memory Window 2
Memory Window 3
Memory Window 4
I/O Window 0
I/O Window 1
Bit 0 — Reserved
This bit must be programmed to ‘0’ for I/O offset.
Bits 7:1 — Offset Address 7:1(I/O)
This register contains the least-significant byte of the quantity that is added to the system
address to determine where in the PC Card’s I/O map the I/O access occurs.
June 1998
ADVANCE DATA BOOK v0.3
GENERAL WINDOW MAPPING
REGISTERS
123