CS5540 Datasheet, PDF (12/22 Pages) Cirrus Logic – LOW POWER LOW VOLTAGE 24- BIT ACD

CS5540
2.3 Power Supply Arrangements
The CS5540 is designed to operate with a total sup-
ply voltage of 3.0 V ± 5%. For maximum flexibili-
ty, separate pins are provided for VA+, VA-, VD+,
and DGND, which is especially useful with
ground-referenced input signals.
Figure 7 illustrates the CS5540 connected with a
single +3.0 V supply for both the analog and digital
sections.
2.4 Clock Generator
The CS5540 includes an oscillator circuit which
can be connected with an external crystal to pro-
vide the master clock for the chip. The chip is de-
signed to operate using a low-cost 32.768 kHz
“tuning fork” type crystal. One lead of the crystal
should be connected to OSC1 and the other to
OSC2. A 10 megohm resistor is required in parallel
with the crystal. Lead lengths should be minimized
to reduce stray capacitance. Note that the converter
will operate with an external (CMOS compatible)
clock with frequencies up to 40kHz, applied to the
OSC1 pin.
2.5 Serial Port Interface
The CS5540’s serial interface consists of three con-
trol lines: CS, SDO, and SCLK.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied to logic
0, the port can function as a three wire interface.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held at logic 0 be-
fore SCLK transitions can be recognized by the
port logic. To accommodate opto-isolators, SCLK
is designed with a Schmitt-trigger input.
2.6 Input Channel Selector
CHS, the Channel Select input, permits the user to
select between AIN1 and AIN2 for data conver-
sions. When CHS = 0, AIN1 is converted. When
CHS = 1, AIN2 is converted. Note that since the
converter continuously converts the input selected
+3.0 V
Analog
Supply
Voltage
Reference
Analog
Signal
Sources
10 Ω
0.1 µF
14
+
13
-
1
2
4
VA+
VREF+
11
VD+
OSC2 ⁹
VREF-
OSC1 ⁸
CS5540
AIN1+
CS ⁵
SDO ¹⁰
AIN1-
6
SCLK
0.1 µF
5 kHz ~ 40 kHz
10 M Ω
Optional Clock
Source
Serial
Data
Interface
16
AIN2+
15 _AIN2-
VA-
3
7
CHS
DGND
12
Channel
Selection
Figure 7. CS5540 Configured with a single +3.0 V Supply
12
DS503PP1