CS3011_09 Datasheet, PDF (12/18 Pages) Cirrus Logic – Precision Low-voltage Amplifier; DC to 1 kHz

CS3011
CS3012
The loop gain plot shown in Figure 17 i llustrates
the unity gain configuration, and indicates how this
is mo dified when using the amplifier in a hig her
gain configuration with compensation. If it is config-
ured for higher gain, for example, 60 dB, the x–axis
will move up by 60 dB (line B). Capacitor C2 adds
a zero and a pole. The modified plot indicates the
effects of introducing the pole and zero due to ca-
pacitor C2 . The pole can be located at any fre-
quency higher than the hand-over frequency, the
zero has to be at a frequency lower than the hand-
over freque ncy so as to provide ade quate ga in
margin. The separation between the pole and the
zero is governed by the closed loop gain. The zero
(z₁) occurs at the intersection o f the –100 dB/de-
cade and –80 dB/decade slopes. The point X in the
figure should be at closed loop gain plus 20 dB
gain margin. The value for C2 = 1/(2πR1p1). Us-
ing p1 = 500 kHz works very well and is indepen-
dent of ga in. As the closed loop ga in is change d,
the zero location is also modified if R1 remains
fixed. Cap acitor C2 ca n be incre ased in value to
limit the amplifier’s rising noise above 1 kHz.
-100 dB/dec
z₁
p₁
-80 dB/dec
X
Margin
B
-20 dB/dec
Desired Closed
Loop Gain
25 kH⁵z^0kH5^z00 kHz ¹2^M.4^HM^z Hz ^5MHz
FREQUENCY
Figure 17. Loop Gain Plot: Unity Gain and with Pole-Zero Compensation
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DS597F6