CS2300-OTP_09 Datasheet, PDF(12/26 Page) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

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CS2300-OTP_09 Datasheet, PDF (12/26 Pages) Cirrus Logic – Fractional-N Clock Multiplier with Internal LCO

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CS2300-OTP

to as wander. In others it may be preferable to remove only higher frequency jitter, allowing the input wan-

der to pass through the PLL without attenuation.

Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-

tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of

the lowest PLL bandwidth setting. See Figure 8.

Wander > 1 Hz

CLK_IN

Jitter

PLL

BW = 1 Hz

PLL_OUT

Wander and Jitter > 1 Hz Rejected

MCLK

LRCK

Subclocks generated

from new clock domain.

LRCK

SCLK

SDATA

Figure 8. Low bandwidth and new clock domain

Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data

are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the

system. See Figure 9. If there is substantial wander on the CLK_IN signal in these applications, it may be

necessary to increase the minimum loop bandwidth allowing this wander to pass through to the CLK_OUT

signal in order to maintain phase alignment. For these applications, it is advised to experiment with the

loop bandwidth settings and choose the lowest bandwidth setting that does not produce system timing

errors due to wandering between the clocks and data synchronous to the CLK_IN domain and those syn-

chronous to the PLL_OUT domain.

Wander < 128 Hz

CLK_IN

Jitter

PLL

PLL_OUT

BW = 128 Hz

Jitter > 128 Hz Rejected

Wander < 128 Hz Passed to Output

MCLK

LRCK

Subclocks and data re-used

from previous clock domain.

LRCK

SCLK

SDATA

Figure 9. High bandwidth with CLK_IN domain re-use

While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is

achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-

rameter.

Referenced Control

Parameter Definition

ClkIn_BW[2:0] .......................âClock Input Bandwidth (ClkIn_BW[2:0])â on page 21

DS844F1

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