CS5374_0910 Datasheet, PDF (11/44 Pages) Cirrus Logic – Dual High-performance Amplifier & ΔΣ Modulator

CS5374
DS862F1
CS5374
DIGITAL CHARACTERISTICS (CONT.)
Parameter
Symbol Min
Master Clock Input
MCLK Frequency
MCLK Duty Cycle
MCLK Rise Time
MCLK Fall Time
MCLK Jitter (in-band or aliased in-band)
MCLK Jitter (out-of-band)
Master Sync Input
MSYNC Setup Time to MCLK Falling
MSYNC Period
MSYNC Hold Time after MCLK Falling
MDATA Output
MDATA Output Bit Rate
MDATA Output One’s Density Range
Full-scale Output Code, Offset Corrected
(Note 23) f_MCLK
-
MCLK_DTC
40
t_RISE
-
t_FALL
-
MCLK_IBJ
-
MCLK_OBJ
-
(Note 24) t_MSS
20
(Note 24) t_MSYNC
40
(Note 24) t_MSH
20
(Note 22)
(Note 25)
f_MDATA
MDAT_1D
MDAT_FS
-
14
0xA2E736
Typ
2.048
-
-
-
-
-
366
976
610
512
-
-
Max
-
60
50
50
300
1
-
-
-
-
86
0x5D18CA
Unit
MHz
%
ns
ns
ps
ns
ns
ns
ns
kbits/s
%
Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically
enters a power-down state. See Power Supply Characteristics for typical power-down timing.
24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge,
synchronization instant (t₀) is on the next MCLK rising edge.
25. Decimated, filtered, and offset-corrected 24-bit output word from the CS5376A digital filter.
MCLK
MSYNC
MDATA
MFLAG
tMSS
tMSH
t0
tMSYNC
1 / fMCLK
1 / fMDATA
Figure 7. MCLK / MSYNC Timing Detail
DS862F1
11