CS4383 Datasheet, PDF (11/40 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Channel D/A Converter

CS4383
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(For KQ T_A = -10 to +70 °C; For BQ T_A = -40 to +85 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC,
C_L = 30 pF)
Parameter
CCLK Clock Frequency
Symbol
Min
f_sclk
-
Max
M------C----L----K---
2
Unit
MHz
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
t_srs
(Note 20)
t_spi
t_csh
t_css
t_scl
500
500
1.0
20
--------1---------
MCLK
-
ns
-
ns
-
µs
-
ns
-
ns
CCLK High Time
t_sch
--------1---------
MCLK
-
ns
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
t_dsu
40
(Note 21)
t_dh
15
(Note 22)
t_r2
-
(Note 22)
t_f2
-
-
ns
-
ns
100
ns
100
ns
Notes: 22. t_spi only needed before first falling edge of CS after RST rising edge. t_spi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For F_SCK < 1 MHz.
RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
C D IN
t _{dsu t dh}
Figure 4. Control Port Timing - SPI Format
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