CS89712 Datasheet, PDF (104/170 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH 10BASE-T ETHERNET CONTROLLER

CS89712
Bit
8:12 or 7:12
13
14
16:31
Description
Frame length: The Frame Length field is the total number of shift clocks required to complete a
data transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit
+ 16 bits result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
SMCKEN: Setting this bit will enable a free running sample clock at twice the programmed ADC
clock frequency to be output on the SMPLCK pin.
TXFRMEN: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC
configuration field will be shifted out to the ADC and depending on the frame length programmed,
a number of bits will be captured from the ADC. If the SYNCIO register is written to with the
TXFRMEN bit low, no ADC transfer will take place, but the Frame length and SMCKEN bits will
be affected.
ADC Configuration Extension: When the ADCCON control bit in the SYSCON3 register = 0,
this field is ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the
SYSCON3 register = 1, this field is the configuration data to be sent to the ADC. The ADC Con-
figuration Extension field length is determined by the value held in the ADC Configuration Length
field (SYNCIO[6:0]).
Table 57. SYNCIO (Continued)
3.13 End Of Interrupt Locations
The ‘End of Interrupt’ locations that follow are written to after the appropriate interrupt has been serviced.
The write is performed to clear the interrupt status bit, so that other interrupts can be serviced. Any value
may be written to these locations.
3.13.1 BLEOI Battery Low End of Interrupt (address 0x8000.0600)
A write to this location clears the interrupt generated by a low battery (falling edge of BATOK with nEXTPWR
high).
3.13.2 MCEOI Media Changed End of Interrupt (address 0x8000.0640)
A write to this location will clear the interrupt generated by a falling edge of the nMEDCHG input pin.
3.13.3 TEOI Tick End of Interrupt Location (address 0x8000.0680)
A write to this location will clear the current pending tick interrupt and tick watch dog interrupt.
3.13.4 TC1EOI TC1 End of Interrupt Location (address 0x8000.06C0)
A write to this location will clear the under flow interrupt generated by TC1.
3.13.5 TC2EOI TC2 End of Interrupt Location (address 0x8000.0700)
A write to this location will clear the under flow interrupt generated by TC2.
3.13.6 RTCEOI RTC Match End of Interrupt (address 0x8000.0740)
A write to this location will clear the RTC match interrupt
3.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt (address 0x8000.0780)
A write to this location will clear the modem status changed interrupt.
104
DS502PP2