WM8259 Datasheet, PDF (10/26 Pages) Wolfson Microelectronics plc – Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output

WM8259
Production Data
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
The WM8259 processes the sampled video signal on either VINP1 or VINP2 with respect to the
video-reset level or an internally/externally generated reference level through the analogue-
processing channel.
This processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 16-bit digital word. The digital output from
the ADC is presented on a 4-bit wide bus.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via a serial interface.
INPUT SAMPLING
The WM8259 has two selectable inputs VINP1 and VINP2, and a single analogue processing
channel and ADC, which can be used in a flexible manner to process both monochrome and line-by-
line colour inputs.
To select between VINP1 and VINP2, register bit INPSEL is used. Default (INPSEL=0) is VINP1.
The two inputs can be shorted together using the register bit INPTIE.
Monochrome: The selected input (VINPx) is sampled, processed by the analogue channel, and
converted by the ADC. The same offset DAC and PGA register values are always applied.
Colour Line-by-Line: VINPx is sampled and processed by the analogue channel before being
converted by the ADC. The gains and offset register values applied to the PGA and offset DAC can
be switched between the independent Red, Green and Blue digital registers (e.g. Red → Green→
Blue → Red…) at the start of each line in order to facilitate line-by-line colour operation. The
INTM[1:0] bits determine which register contents are applied (see Table 1) to the PGA and offset
DAC. By using the INTM[1:0] bits to select the desired register values only one register write is
required at the start of each new colour line.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8259 VINPx pin lies within the valid input range (0V to
AVDD) the CCD output signal is usually level shifted by coupling through a capacitor, CIN. When
active, the RLC circuit clamps the WM8259 side of this capacitor to a suitable voltage during the
CCD reset period. The RLCINT register bit controls is used to activate the Reset Level Clamp circuit.
A typical input configuration is shown in Figure 4. The Timing Control Block generates a clamp pulse,
CL, from MCLK and VSMP (when RLCINT is high). When CL is active the voltage on the WM8259
side of CIN, at VINP, is forced to the VRLC/VBIAS voltage (VVRLC) by switch 1. When the CL pulse
turns off, the voltage at VINP initially remains at VVRLC but any subsequent variation in sensor voltage
(from reset to video level) will couple through CIN to VINP.
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to
the CDS/non-CDS Processing section.
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PD Rev 4.2 April 2007
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