CS5464_11 Datasheet, PDF (10/46 Pages) Cirrus Logic – Three-channel, Single-phase Power/Energy IC

CS5464
DIGITAL CHARACTERISTICS
• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
• VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.
• DCLK = 4.096 MHz.
Parameter
Symbol Min
Master Clock Characteristics
Master Clock Frequency
Internal Gate Oscillator (Note 11) DCLK
2.5
Master Clock Duty Cycle
40
CPUCLK Duty Cycle
(Note 12 and 13)
40
Filter Characteristics
Phase Compensation Range
(60 Hz, OWR = 4000 Hz)
-5.4
Input Sampling Rate
DCLK = MCLK/K
-
Digital Filter Output Word Rate
(Both channels) OWR
-
High-pass Filter Corner Frequency
-3 dB
-
Full-scale DC Calibration Range (Referred to Input) (Note 14) FSCR
25
Channel-to-channel Time-shift Error
(Note 15)
Input/Output Characteristics
High-level Input Voltage
All Pins Except XIN and SCLK and RESET
XIN ^VIH
SCLK and RESET
0.6 VD+
(VD+) – 0.5
0.8VD+
Low-level Input Voltage (VD = 5 V)
All Pins Except XIN and SCLK and RESET
XIN ^VIL
-
-
SCLK and RESET
-
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN ^VIL
-
-
SCLK and RESET
-
High-level Output Voltage
I_out = +5 mA V_OH (VD+) - 1.0
Low-level Output Voltage
I_out = -5 mA (VD = +5V) V_OL
-
I_out = -2.5 mA (VD = +3.3V)
-
Input Leakage Current
(Note 16) I_in
-
3-state Leakage Current
I_OZ
-
Digital Output Pin Capacitance
C_out
-
Typ
4.096
-
-
-
DCLK/8
DCLK/1024
0.5
-
1.0
-
-
-
-
-
-
-
-
-
-
-
-
±1
-
5
Max
20
60
60
+5.4
-
-
-
100
-
-
-
0.8
1.5
0.2VD+
0.48
0.3
0.2VD+
-
0.4
0.4
±10
±10
-
Unit
MHz
%
%
°
Hz
Hz
Hz
%FS
µs
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
pF
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the input.
15. Configuration register (Config) bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
10
DS682F3