CS4352 Datasheet, PDF (10/19 Pages) Cirrus Logic – 192 kHz Stereo DAC with 2 Vrms Line Out

4. APPLICATIONS
CS4352
4.1 Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode is
auto-detected.
The CS4352 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK fre-
quency, falls within one of the ranges illustrated in Table 1. Sample rates outside the specified range for
each mode are not supported.
Input Sample Rate (F_S)
4 kHz - 54 kHz
Single-Speed Mode
84 kHz - 108 kHz
Double-Speed Mode
170 kHz - 216 kHz
Quad-Speed Mode
Table 1. CS4352 Auto-Detect
Mode
4.2 System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (F_s), must be synchronously derived from the
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-
dio sample rates and the required MCLK frequency, are illustrated in Tables 2-4.
Refer to Section 4.3 for the required SCLK timing associated with the selected Digital Interface Format and
to “Switching Specifications - Serial Audio Interface” on page 7 for the maximum allowed clock frequencies.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
384x
12.2880
16.9344
18.4320
MCLK (MHz)
512x
16.3840
22.5792
24.5760
768x
24.5760
33.8688
36.8640
Table 2. Single-Speed Mode Standard Frequencies
1024x
32.7680
45.1584
49.1520
Sample Rate
(kHz)
88.2
96
128x
11.2896
12.2880
192x
16.9344
18.4320
MCLK (MHz)
256x
22.5792
24.5760
384x
33.8688
36.8640
Table 3. Double-Speed Mode Standard Frequencies
512x
45.1584
49.1520
Sample Rate
(kHz)
176.4
192
128x
22.5792
24.5760
MCLK (MHz)
192x
33.8688
36.8640
256x
45.1584
49.1520
Table 4. Quad-Speed Mode Standard Frequencies
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