PA15FL_10 Datasheet, PDF (1/5 Pages) Cirrus Logic – High Voltage Power Operational Amplifiers

® Product
PA^IP1^nr5^noodF^vuL^act,^ti P^{oI nn}A^{n o}1^v5^aF^{t i}L^{o n}A^{F r o m}
From
PA15FPLA1•5PFLA•1P5AF15LFALA
High Voltage Power Operational Amplifiers
FEATURES
• HIGH VOLTAGE — 450V (±225V)
• LOW COST
• LOW QUIESCENT CURRENT — 3.0mA MAX
• HIGH OUTPUT CURRENT — 200mA
• PROGRAMMABLE CURRENT LIMIT
APPLICATIONS
• PIEZOELECTRIC POSITIONING
• HIGH VOLTAGE INSTRUMENTATION
• ELECTROSTATIC TRANSDUCERS
• PROGRAMMABLE POWER SUPPLIES UP TO 440V
DESCRIPTION
The PA15FL is a high voltage, low quiescent current MOSFET
operational amplifier designed as a low cost solution for driving
continuous output currents up to 200mA and pulse currents up
to 350mA into capacitive loads.The safe operating area (SOA)
has no second breakdown limitations and can be observed for
all type loads by choosing an appropriate current limiting resistor.
The MOSFET input stage has integrated static and differential
mode protection. The MOSFET output stage is biased AB for
linear operation. External compensation provides flexibility
in choosing bandwidth and slew rate for the application. The
10-pin power SIP package is electrically isolated.
EQUIVALENT SCHEMATIC
6
+V_S
R1 R2
C1
R3
Q1
Q2
Q6
Q5
8
9 ^CC2
CC1
1
–IN ^R5
R8
R6
R9
2
+IN
Q15
R11
–V_S
5
Q3
R4
Q4
Q8
Q11
Q13
Q12
ILIM
7
R7
10
OUT
Q14
R10
Q16
R12
TYPICAL APPLICATION
R_F
+V_S
10-PIN SIP
PACKAGE STYLE FL
Formed leads available
See package style FU
R_IN
COMPUTER
FOCUS
COMMAND
VOLTAGE
6
1
PIEZO DRIVE
10
PA15FL
V_OUT
2
7
5
R_CL
-V_S
LOW POWER, PIEZOELECTRIC POSITIONING
Piezo positioning may be applied to the focusing of segment-
ed mirror systems. The composite mirror may be composed of
hundreds of elements, each requiring focusing under computer
control. In such complex systems the PA15FL reduces the
costs of power supplies and cooling with its advantages of low
cost and low quiescent power consumption while increasing
circuit density with the SIP package.
EXTERNAL CONNECTIONS
1 2 3 4 5 6 7 8 9 10
NC NC –V_S +V_S I_LIM
C_C2 C_C1 OUT
R_C
–IN +IN
C_C
R _CL
PHASE COMPENSATION
GAIN
≥1
≥ 10
3C3p^C f
OPEN
1RK^CΩ
OPEN
R_CL ≅
.6
I_CL
PA15_wF_wL_wU_.cirrus.com
Copyright © Cirrus Logic, Inc. 2010
(All Rights Reserved)
MAR 2010₁
APEX − PA15FLUREVE