CS5560 Datasheet, PDF (1/32 Pages) Cirrus Logic – ±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ΔΣ ADC

7/31/07
CS5560
±2.5 V / 5 V, 50 kSps, 24-bit, High-throughput ∆Σ ADC
Features & Description
‰ Differential Analog Input
‰ On-chip Buffers for High Input Impedance
‰ Conversion Time = 20 µS
‰ Settles in One Conversion
‰ Linearity Error = 0.0007%
‰ Signal-to-Noise = 110 dB
‰ 24 Bits, No Missing Codes
‰ Self-calibration:
- Maintains accuracy over time & temperature.
‰ Simple three/four-wire serial interface
‰ Power Supply Configurations:
- Analog: +5V/GND; IO: +1.8V to +3.3V
- Analog: ±2.5V; IO: +1.8V to +3.3V
‰ Power Consumption:
- ADC Input Buffers On: 85 mW
- ADC Input Buffers Off: 70 mW
General Description
The CS5560 is a single-channel, 24-bit analog-to-digital
converter capable of 50 kSps conversion rate. The input
accepts a fully differential analog input signal. On-chip
buffers provide high input impedance for both the AIN in-
puts and the VREF+ input. This significantly reduces the
drive requirements of signal sources and reduces errors
due to source impedances. The CS5560 is a delta-sigma
converter capable of switching multiple input channels at
a high rate with no loss in throughput. The ADC uses a
low-latency digital filter architecture. The filter is designed
for fast settling and settles to full accuracy in one conver-
sion. The converter's 24-bit data output is in serial form,
with the serial port acting as either a master or a slave. The
converter is designed to support bipolar, ground-refer-
enced signals when operated from ±2.5V analog supplies.
The CS5560 uses self-calibration to achieve low offset and
gain errors. The converter achieves a S/N of 110 dB. Lin-
earity is ±0.0007% of full scale.
The converter can operate from an analog supply of 0-5V
or from ±2.5V. The digital interface supports standard log-
ic operating from 1.8, 2.5, or 3.3 V.
ORDERING INFORMATION:
See Ordering Information on page 32.
V1+
V2+
VL
VREF+
VREF-
AIN+
AIN-
ADC
CS5560
DIGITAL
FILTER
LOGIC
SERIAL
INTERFACE
SMODE
CS
SCLK
SDI
SDO
RDY
BUFEN
OSC/CLOCK
GENERATOR
CALIBRATION
MICROCONTROLLER
SLEEP
RST
CONV
CAL
BP/UP
MCLK
V1-
V2-
DCR
VLR
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
AUG ‘07
DS713A5