CS5378_08 Datasheet, PDF(1/88 Page) Cirrus Logic – Low-power Single-channel Decimation Filter

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

CS5378_08 Datasheet, PDF (1/88 Pages) Cirrus Logic – Low-power Single-channel Decimation Filter

CS5378

Low-power Single-channel Decimation Filter

Features

z Single-channel Digital Decimation Filter

Â Multiple On-chip FIR and IIR Coefficient Sets

Â Programmable Coefficients for Custom Filters

Â Synchronous Operation

z Integrated PLL for Clock Generation

Â 1.024 MHz, 2.048 MHz, or 4.096 MHz Input

Â Standard Clock or Manchester Input

z Selectable Output Word Rate

Â 4000, 2000, 1000, 500, 333, 250 SPS

Â 200, 125, 100, 50, 40, 25, 20, 10, 5, 1 SPS

z Digital Gain and Offset Corrections

z Test DAC Bit-stream Generator

Â Digital Sine Wave Output

z Time Break Controller, General-purpose I/O

z Microcontroller or EEPROM Configuration

z Small-footprint, 28-pin SSOP Package

z Low Power Consumption

Â 16 mW at 500 SPS OWR

z Flexible Power Supplies

Â I/O Interface and PLL: 3.3 V or 5.0 V

Â Digital Logic Core: 2.5 V, 3.3 V or 5.0 V

Description

The CS5378 is a multi-function digital filter utilizing a low-

power signal processing architecture to achieve efficient

filtering for a delta-sigma-type modulator. By combining

the CS5378 with a CS3301A/02A differential amplifier

and a CS5373A modulator + test DAC, a synchronous

high-resolution, self-testing, single-channel measure-

ment system can be designed quickly and easily.

Digital filter coefficients for the CS5378 FIR and IIR filters

are included on-chip for a simple setup, or they can be

programmed for custom applications. Selectable digital

filter decimation ratios produce output word rates from

4000 SPS to 1 SPS, resulting in measurement band-

widths ranging from 1600 Hz down to 400 mHz when

using the on-chip coefficient sets.

The CS5378 includes integrated peripherals to simplify

system design: a low-jitter PLL for standard clock or

Manchester inputs, offset and gain corrections, a test

DAC bit stream generator, a time break controller, and

eight general-purpose I/O pins.

ORDERING INFORMATION

See page 86.

Serial Interface

Decimation and

Filtering Engine

Modulator Data Interface

PLL, Clock Generation

Reset, Synchronization

Time Break Controller

Test Bit Stream

Controller

GPIO

General Purpose I/O

CLK

MCLK

RESET

SYNC

MSYNC

TIMEB

TBSDATA

GPIO7:BOOT

GPIO6:PLL2

GPIO5:PLL1

GPIO4:PLL0

GPIO3

GPIO2

GPIO1

GPIO0

http://www.cirrus.com

SEP â08

DS639F2

▷